BT860 datasheet(13/111 Pages) CONEXANT

13 / 111 page

Bt860/861

1.0 Functional Description

Multiport YCrCb to NTSC/PAL /SECAM

1.1 Pin Descriptions

D860DSA

Conexant

1-3

GRAPHIC AND BLENDING PINS

OSD[7:0]

40-39, 36-31

Dedicated graphic overlay port (TTL compatible.) Accepts pixel data in 8-bit YCrCb

4:2:2 format. Data is latched on the rising edge of the system clock(1) (2).

ALPHA[1:0]

30-29

Alpha blend pins. Provides for 1-, 2-, or 4-bit external blend selection between video

and graphic overlay data. Data is latched on the rising edge of the system clock(1) (2).

TELETEXT AND SERIAL CONTROL INTERFACE

TTXDAT

Teletext data input (TTL compatible)(1).

TTXREQ

Teletext request output (TTL compatible).

ALTADDR

I/O

Alternate slave address input (TTL compatible). This pin is sampled immediately

following a power-up or pin reset. A logical 1 corresponds to write address of 0x88

and a read address of 0x89, while a logical 0 corresponds to a write address of 0x8A

and a read address of 0x8B. See Chapter 5.0, for more detail. This pin also provides

special SCART signals when register field SCART_SEL

≠00.

SID

I/O

Serial programming interface data input/output (TTL compatible). Data is written to

and read from the device via this serial bus.

SIC

Serial programming interface clock input (TTL compatible). The maximum clock rate is

400 kHz.

ANALOG VIDEO

DACA

DAC A output. See Table 3-9.

DACB

DAC B output. See Table 3-9.

DACC

DAC C output. See Table 3-9.

DACD

DAC D output. See Table 3-9.

DACE

DAC E output. See Table 3-9.

DACF

DAC F output. See Table 3-9.

FSADJ1

FSADJ2

I53

Full-scale adjust control pin. Resistors RSET1 and RSET2 connected between these

pins and AGND control the full-scale output current of the DACs. For standard

operation, use the nominal values shown under Recommended Operating

Conditions. FSADJ1 controls DACs A/B/C and FSADJ2 controls DACs D/E/F.

VREF

Voltage reference pin. A 1.0 µF ceramic capacitor must be used to decouple this pin

to AGND. The capacitor must be as close to the device as possible to keep lead

lengths to an absolute minimum.

COMP1

COMP2

O54

Compensation pin. A 0.1 µF ceramic capacitor must be used to decouple this pin to

VAA. The capacitor must be as close to the device as possible to keep lead lengths

to an absolute minimum.

VBIAS1

VBIAS2

O56

DAC bias voltage. Use a 0.1 µF ceramic capacitor to bypass this pin to AGND; the

capacitor must be as close to the device as possible to keep lead lengths to an

absolute minimum.

Table 1-1. Pin Assignments (2 of 3)

Pin Name

I/O

Pin #

Description

BT860 Datasheet(PDF) 13 Page - Synaptics Incorporated.

BT860 Datasheet(HTML) 13 Page - Synaptics Incorporated.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL