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LAN89730 Datasheet(PDF) 177 Page - Microchip Technology |
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LAN89730 Datasheet(HTML) 177 Page - Microchip Technology |
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177 / 218 page  2013-2015 Microchip Technology Inc. DS60001348A-page 177 LAN89730 6.5 PHY Registers The PHY registers are not memory mapped. These registers are accessed indirectly through the MAC via the MII Access Register (MII_ACCESS) and MII Access Register (MII_ACCESS). An index is used to access individual PHY registers. PHY Register Indexes are shown in Table 6-6, "PHY Control and Status Register" below. Note: The NASR (Not Affected by Software Reset) designation is only applicable when bit 15 of the PHY Basic Control Register (Reset) is set. TABLE 6-6: PHY CONTROL AND STATUS REGISTER Index (In Decimal) Register Name 0 Basic Control Register 1 Basic Status Register 2 PHY Identifier 1 Register 3 PHY Identifier 2 Register 4 Auto Negotiation Advertisement Register 5 Auto Negotiation Link Partner Ability Register 6 Auto Negotiation Expansion Register 16 EDPD NLP/Crossover TimeRegister 17 Mode Control/Status Register 18 Special Modes Register 26 Symbol Error Counter Register 27 Special Control/Status Indications Register 29 Interrupt Source Flag Register 30 Interrupt Mask Register 31 PHY Special Control/Status Register |
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