MCP79412 datasheet(37/66 Pages) MICROCHIP

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DS20002266H-page 37

MCP79410/MCP79411/MCP79412

FIGURE 6-2:

SRAM/RTCC SEQUENTIAL WRITE

6.1.3

SRAM/RTCC REGISTER CURRENT

ADDRESS READ

The MCP7941X contains an address counter that

maintains the address of the last byte accessed,

internally incremented by one. Therefore, if the

previous read access was to address n (n is any legal

address), the next current address read operation

would access data from address n + 1.

Upon receipt of the control byte with R/W bit set to ‘1’,

the MCP7941X issues an Acknowledge and transmits

the 8-bit data word. The master will not acknowledge

the transfer but does generate a Stop condition and the

MCP7941X discontinues transmission (Figure 6-3).

FIGURE 6-3:

SRAM/RTCC CURRENT

ADDRESS READ

6.1.4

SRAM/RTCC REGISTER RANDOM

READ

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, first the address must be

set. This is done by sending the address to the

MCP7941X as part of a write operation (R/W bit set to

‘0’). After the address is sent, the master generates a

Start condition following the Acknowledge. This

terminates the write operation, but not before the

internal Address Pointer is set. Then, the master issues

the control byte again but with the R/W bit set to a ‘1’.

The MCP7941X will then issue an Acknowledge and

transmit the 8-bit data word. The master will not

acknowledge the transfer but it does generate a Stop

condition which causes the MCP7941X to discontinue

transmission (Figure 6-4). After a random Read

command, the internal address counter will point to the

address location following the one that was just read.

6.1.5

SRAM/RTCC REGISTER

SEQUENTIAL READ

Sequential reads are initiated in the same way as a

random read except that after the MCP7941X transmits

the first data byte, the master issues an Acknowledge

as opposed to the Stop condition used in a random

read. This Acknowledge directs the MCP7941X to

transmit the next sequentially addressed 8-bit word

(Figure 6-5). Following the final byte transmitted to the

master, the master will NOT generate an Acknowledge

but will generate a Stop condition. To provide

sequential reads, the MCP7941X contains an internal

Address Pointer which is incremented by one at the

completion of each operation. This Address Pointer

allows the entire memory block to be serially read

during one operation.

Because the RTCC registers and SRAM are separate

blocks, reading past the end of each block will cause

the Address Pointer to roll over to the beginning of the

same block. Specifically, the Address Pointer will roll

over from 0x1F to 0x00, and from 0x5F to 0x20.

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

ADDRESS

BYTE

DATA BYTE 0

DATA BYTE N

S 1 101

111

Note:

The Address Pointer is shared between

the SRAM/RTCC registers and the

EEPROM.

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA

BYTE

11 1

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