Product Operation

The current is sampled by the delta-sigma modulator, as il-

lustrated in

Figure 4. The pulse density output of the

delta-sigma modulator is digitally filtered. The digital output

is then compared to the output of a digital ramp generator.

This produces a PWM output. The duty cycle of the PWM

output is proportional to the amount of current flowing. A duty

cycle of 50% indicates zero current flow. If the current is flow-

ing in positive direction, the duty cycle will be greater than

50%. Conversely, the duty cycle will be less than 50% for

currents flowing in the negative direction. A duty cycle of

95.5% (4.5%) indicates the current is at I

can sense currents from −I

1.0A or 2.0A. The sense current is given by:

I

where D is the duty cycle of the PWM waveform, and I

the full scale current (1.00A or 2.00A). Similarly, the duty

cycle is given by:

D=[I

For quick reference, see the Conversion Table in

Table 1.

In this IC, the current is averaged over 50 msec time slots.

Hence, momentary current surges of less than 50 msec are

tolerated.

This is a sampled data system which requires an

anti-aliasing filter, provided by the filter capacitor.

The delta-sigma modulator converts the sensed current to

the digital domain. This allows digital filtering, and provides

immunity to current and noise spikes. This type of filtering

would be difficult or impossible to accomplish on an IC with

analog components.

The user also needs to specify the full scale value. See the

Ordering Information table for details.

DS101249-10

FIGURE 4. Functional block diagram of LM3822

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