HT48R50A datasheet(12/46 Pages) HOLTEK

12 / 46 page

HT48R50A-1

Rev. 1.10

July 2, 2001

Accumulator

The accumulator is closely related to ALU oper-

ations. It is also mapped to location 05H of the

data memory and can carry out immediate data

operations. The data movement between two

data memory locations must pass through the

accumulator.

Arithmetic and logic unit - ALU

This circuit performs 8-bit arithmetic and logic

operations. The ALU provides the following func-

tions:

· Arithmetic operations (ADD, ADC, SUB,

SBC, DAA)

· Logic operations (AND, OR, XOR, CPL)

· Rotation (RL, RR, RLC, RRC)

· Increment and Decrement (INC, DEC)

· Branch decision (SZ, SNZ, SIZ, SDZ ....)

The ALU not only saves the results of a data op-

eration but also changes the status register.

Status register - STATUS

This 8-bit register (0AH) contains the zero flag

(Z), carry flag (C), auxiliary carry flag (AC),

overflow flag (OV), power down flag (PD), and

watchdog time-out flag (TO). It also records the

status information and controls the operation

sequence.

With the exception of the TO and PD flags,

bits in the status register can be altered by

instructions like most other registers. Any

data written into the status register will not

change the TO or PD flag. In addition opera-

tions related to the status register may give

different results from those intended. The

TO flag can be affected only by system

power-up, a WDT time-out or executing the

"CLR WDT" or "HALT" instruction. The PD

flag can be affected only by executing the

"HALT" or "CLR WDT" instruction or during

a system power-up.

The Z, OV, AC and C flags generally reflect the

status of the latest operations.

In addition, on entering the interrupt sequence

or executing the subroutine call, the status reg-

ister will not be pushed onto the stack automat-

ically. If the contents of the status are

important and if the subroutine can corrupt the

status register, precautions must be taken to

save it properly.

Labels

Bits

Function

C is set if the operation results in a carry during an addition operation or if a bor-

row does not take place during a subtraction operation; otherwise C is cleared. C

is also affected by a rotate through carry instruction.

AC is set if the operation results in a carry out of the low nibbles in addition or no

borrow from the high nibble into the low nibble in subtraction; otherwise AC is

cleared.

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is

cleared.

OV is set if the operation results in a carry into the highest-order bit but not a

carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

PD is cleared by system power-up or executing the "CLR WDT" instruction. PD

is set by executing the "HALT" instruction.

TO is cleared by system power-up or executing the "CLR WDT" or "HALT" in-

struction. TO is set by a WDT time-out.

Unused bit, read as "0"

Status register

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