HT48R50A datasheet(14/46 Pages) HOLTEK

14 / 46 page

HT48R50A-1

Rev. 1.10

July 2, 2001

abled, the stack is not full and the T1F is set, a

subroutine call to location 0CH will occur. The

related interrupt request flag (T1F) will be re-

set and the EMI bit cleared to disable further

interrupts.

During the execution of an interrupt subroutine,

other interrupt acknowledge signals are held

until the "RETI" instruction is executed or the

EMI bit and the related interrupt control bit are

set to 1 (if the stack is not full). To return from

the interrupt subroutine, "RET" or "RETI" may

be invoked. RETI will set the EMI bit to enable

an interrupt service, but RET will not.

Interrupts, occurring in the interval between

the rising edges of two consecutive T2 pulses,

will be serviced on the latter of the two T2

pulses, if the corresponding interrupts are en-

abled. In the case of simultaneous requests the

following table shows the priority that is ap-

plied. These can be masked by resetting the

EMI bit.

No. Interrupt Source Priority Vector

External Interrupt

04H

Timer/event

counter 0 overflow

08H

Timer/event

counter 1 overflow

0CH

The Timer/Event Counter 0/1 interrupt request

flag (/T1F), external interrupt request flag

(EIF), enable Timer/Event Counter 0/1 inter-

rupt bit (ET0I/ET1I), enable external interrupt

bit (EEI) and enable master interrupt bit (EMI)

constitute an interrupt control register (INTC)

which is located at 0BH in the data memory.

EMI, EEI, ET0I and ET1I are used to control

the enabling/disabling of interrupts. These bits

prevent the requested interrupt from being ser-

viced. Once the interrupt request flags (T0F,

T1F, EIF) are set, they will remain in the INTC

cleared by a software instruction.

It is recommended that a program does not

use the "CALL subroutine" within the inter-

rupt subroutine. Interrupts often occur in an

unpredictable manner or need to be serviced

immediately in some applications. If only one

stack is left and enabling the interrupt is not

well controlled, the original control sequence will

be damaged once the "CALL" operates in the in-

terrupt subroutine.

Oscillator configuration

There are 3 oscillator circuits in the

microcontroller.

All of them are designed for system clocks,

namely the external RC oscillator, the external

Crystal oscillator and the internal RC

oscillator, which are determined by ROM code

option. No matter what oscillator type is se-

lected, the signal provides the system clock.

The HALT mode stops the system oscillator

and ignores an external signal to conserve

power.

S yst e m C l o ck/ 4

8- bi t C ou nt e r

W D T P r e sca l e r

7- bi t C ou nt e r

8 - to - 1 M U X

W D T T i m e - out

WS 0 ~ WS 2

RO M

C ode

Op t i o n

Se l e c t

WD T

OS C

RT C O S C

Watchdog Timer

C r yst a l O sci l l a t o r

( I nc l ude 32 768H z )

R C O s c illa t o r

OS C 1

OS C 2

N M O S O pen D r a i n

OS C 2

f SY S /4

470p F

V DD

OS C 1

System oscillator

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