M30LW128D datasheet(11/57 Pages) STMICROELECTRONICS

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M30LW128D

Status - the pin gives a pulsing signal to indicate

the end of a Program or Block Erase operation.

After power-up or reset the STS pin is configured

in Ready/Busy mode. The pin can be configured

for Status mode using the Configure STS com-

mand.

When the Program/Erase Controller is idle, or sus-

pended, STS can float High through a pull-up re-

sistor. The use of an open-drain output allows the

STS pins from several devices to be connected to

a single pull-up resistor (a Low will indicate that

one, or more, of the memories is busy).

STS is not Low during a reset unless the reset was

applied when the Program/Erase controller was

active.

The STS signal is not available with the LFBGA88

package.

Program/Erase Enable (VPEN). The

Program/

Erase Enable input, VPEN, is used to protect all

blocks, preventing Program and Erase operations

from affecting their data.

Program/Erase Enable must be kept High during

all Program/Erase Controller operations, other-

wise the operations is not guaranteed to succeed

and data may become corrupt.

VDD Supply Voltage. VDD provides the power

supply to the internal core of the device. It is the

main power supply for all operations (Read, Pro-

gram and Erase).

VDDQ Supply Voltage. VDDQ provides the power

supply to the I/O pins and enables all Outputs to

be powered independently from VDD. VDDQ can be

tied to VDD or can use a separate supply.

It is recommended to power-up and power-down

VDD and VDDQ together to avoid any condition that

would result in data corruption.

VSS Ground. Ground, VSS, is the reference for

the core power supply. It must be connected to the

system ground.

VSSQ Ground. VSSQ ground is the reference for

the input/output circuitry driven by VDDQ. VSSQ

must be connected to VSS.

Note: Each device in a system should have

VDD and VDDQ decoupled with a 0.1µF ceramic

capacitor close to the pin (high frequency, in-

herently low inductance capacitors should be

as close as possible to the package). See Fig-

ure 10, AC Measurement Load Circuit.

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