M30LW128D datasheet(15/57 Pages) STMICROELECTRONICS

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M30LW128D

BUS OPERATIONS

There are 6 bus operations that control each mem-

ory. Each of these is described in this section, see

Tables 4, Bus Operations, for a summary.

On Power-up or after a Hardware Reset the device

defaults to Read Array mode (Page Read).

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the device and do

not affect bus operations.

Bus Read. Bus Read operations read from the

memory cells, or specific registers (Electronic Sig-

nature, Status Register, CFI and Block Protection

Status) in the Command Interface.

A valid bus operation involves setting the desired

address on the Address inputs, enabling the de-

vice (refer to Table 3), applying a Low signal, VIL,

to Output Enable and keeping Write Enable High,

VIH.

The Data Inputs/Outputs will output the value, see

Figure 11, Bus Read AC Waveforms, and Table

16, Bus Read AC Characteristics, for details of

when the output becomes valid.

Page Read. Page Read operations are used to

read from several addresses within the same

memory page.

Each memory page is a 4 Words or 8 Bytes and

has the same A3-A22. In x8 mode only A0, A1 and

A2 may change, in x16 mode only A1 and A2 may

change.

Valid bus operations are the same as Bus Read

operations but with different timings. The first read

operation within the page has identical timings,

subsequent reads within the same page have

much shorter access times. If the page changes

then the normal, longer timings apply again. See

Figure 12, Page Read AC Waveforms and Table

17, Page Read AC Characteristics for details on

when the outputs become valid.

Bus Write. Bus Write operations write to the

Command Interface in order to send commands to

the device or to latch addresses and input data to

program.

A valid Asynchronous Bus Write operation begins

by setting the desired address on the Address In-

puts and enabling the device (refer to Chip Enable

section).

Both the Address Inputs and Data Input/Outputs

are latched by the Command Interface on the ris-

ing edge of Write Enable or Chip Enable, whichev-

er occurs first.

Output Enable must remain High, VIH, during the

whole Bus Write operation. See Figures 13, and

14, Write AC Waveforms, and Tables 18 and 19,

Write and Chip Enable Controlled Write AC Char-

acteristics, for details of the timing requirements.

Output Disable. The Data Inputs/Outputs are in

the high impedance state when the Output Enable

is High.

Standby. When Chip Enable is High, VIH, the de-

vice enters Standby mode and the Data Inputs/

Outputs pins are placed in the high impedance

state regardless of Output Enable or Write Enable.

The Supply Current is reduced to the Standby

Supply Current, IDD1.

During Program or Erase operations the device

will continue to use the Program/Erase Supply

Current, IDD3, for Program or Erase operations un-

til the operation completes.

Automatic Low Power. If there is no change in

the state of the bus for a short period of time during

Asynchronous Bus Read operations the device

enters Auto Low Power mode where the internal

Supply Current is reduced to the Auto-Standby

Supply Current, IDD5. The Data Inputs/Outputs will

still output data if a Bus Read operation is in

progress.

Automatic Low Power is only available in Asyn-

chronous Read modes.

Power-Down. The device is in Power-Down

mode when Reset/Power-Down, RP, is Low. The

power consumption is reduced to the Power-Down

level, IDD2, and the outputs are high impedance,

independent of Chip Enable, Output Enable or

Write Enable.

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