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OCX160 Datasheet(PDF) 21 Page - List of Unclassifed Manufacturers

Part # OCX160
Description  OCX160 Crosspoint Switch
PDF  44 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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OCX160 Crosspoint Switch—Preliminary Data Sheet
I-Cube, Inc.
[Rev. 1.6] 2/20/01
21
2. Pin Description
NOTES:
1.
Dedicated differential input buffers can receive both LVDS and LVPECL voltage levels using
3.3V supply.
2.
VDD.PAD is 2.5V for LVDS outputs or 3.3V for LVPECL outputs.
3.
Dedicated differential output buffers can be biased using different supplies for V
DD.PAD and
external resistors to support both LVDS and LVPECL output voltage levels.
4.
The LVTTL control, JTAG pins, and differential input ports are 3.3V—they are not 5V tolerant.
5.
The differential output pins powered from 2.5V are 3.3V tolerant.
Table 12
OCX160 Pin Description
Pin Name
# of Pins
Type
Description
INP[79:0]
80
Input
Non-inverting differential input signals
INN[79:0]
80
Input
Inverting differential input signals
OUTP[79:0]
80
Output
Non-inverting differential input signals
OUTN[79:0]
80
Output
Inverting differential input signals
CLKP
1
Input
Non-inverting differential Global Clock
CLKN
1
Input
Inverting differential Global Clock
OE#
1
Input
Global Output Enable
HW_RST#
1
Input
Hardware Reset
UPDATE#
1
Input
Global Update
RC Pins
RCA[6:0]
7
Input
RapidConfigure Address A
RCB[6:0]
7
Input
RapidConfigure Address B
RCO[4:0]
5
Output
RapidConfigure Readback
RCI[3:0]
4
Input
RapidConfigure Instruction Bits
RC_CLK#
1
Input
RapidConfigure Clock
RC_EN#
1
Input
RapidConfigure Cycle Enable
JTAG Pins
TCK
1
Input
JTAG Test Clock
TMS
1
Input
JTAG Test Mode Select
TDI
1
Input
JTAG Test Data In
TRST#
1
Input
JTAG Test Reset
TDO
1
Output
JTAG Test Data Out
Power and Ground Pins
VDD.CORE
12
2.5V Power
Core Voltage
VDD.PAD
(2, 3)
8
2.5V or 3.3V Power
Differential Output Buffer Voltage
VDD.IN
(1, 4)
8
3.3V Power
LVTTL Control pins Voltage and Differential Input
Buffer Voltage
VSS
36
Ground
Ground



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