The LM4701 possesses a mute and standby function with in-

ternal logic gates that are half-supply referenced. Thus, to

enable either the mute or standby function, the voltage at

these pins must be a minimum of 2.5V above half-supply. In

single-supply systems, devices such as microprocessors

and simple logic circuits used to control the mute and

standby functions, are usually referenced to ground, not

half-supply. Thus, to use these devices to control the logic

circuitry of the LM4701, a “level shifter”, like the one shown

in

Figure 5, must be employed. A level shifter is not needed

in

a

split-supply

configuration

since

ground

is

also

half-supply.

When the voltage at the Logic Input node is 0V, the 2N3904

is “off” and thus resistor R

the supply. This enables the mute or standby function. When

the Logic Input is 5V, the 2N3904 is “on” and consequently,

the voltage at the collector is essentially 0V. This will disable

the mute or standby function, and thus the amplifier will be in

its normal mode of operation. R

ates an RC time constant that reduces transients when the

mute or standby functions are enabled or disabled. Addition-

ally, R

gates of the LM4701 which insures device reliability. Refer to

the Mute Mode and Standby Mode sections in the Applica-

tion Information section for a more detailed description of

these functions.

CLICKS AND POPS

In the typical application of the LM4701 as a split-supply au-

dio power amplifier, the IC exhibits excellent “click” and “pop”

performance when utilizing the mute and standby functions.

In addition, the device employs Under-Voltage Protection,

which eliminates unwanted power-up and power-down tran-

sients. The basis for these functions are a stable and con-

stant half-supply potential. In a split-supply application,

ground is the stable half-supply potential. But in a

single-supply application, the half-supply needs to charge up

just like the supply rail, V

This makes the task of attaining a clickless and popless

turn-on more challenging. Any uneven charging of the ampli-

fier inputs will result in output clicks and pops due to the dif-

ferential input topology of the LM4701.

To achieve a transient free power-up and power-down, the

voltage seen at the input terminals should be ideally the

same. Such a signal will be common-mode in nature, and

will be rejected by the LM4701. In

Figure 3, the resistor R

INP

serves to keep the inputs at the same potential by limiting the

voltage difference possible between the two nodes. This

should significantly reduce any type of turn-on pop, due to an

uneven charging of the amplifier inputs. This charging is

based upon a specific application loading and thus, the sys-

tem designer may need to adjust these values for optimum

performance.

As shown in

Figure 3, the resistors labeled R

the LM4701 off the half-supply node at the emitter of the

2N3904. But due to the input and output coupling capacitors

in the circuit, along with the negative feedback, there are two

different values of R

sistors bring up the inputs at the same rate resulting in a pop-

less turn-on. Adjusting these resistors values slightly may re-

duce pops resulting from power supplies that ramp

extremely quick or exhibit overshoot during system turn-on.

AUDIO POWER AMPLlFIER DESIGN

Design a 25W/8

Ω Audio Amplifier

Given:

Power Output

25 Wrms

Load Impedance

8

Ω

Input Level

1 Vrms(max)

Input Impedance

47 k

Ω

Bandwidth

A designer must first determine the power supply require-

ments in terms of both voltage and current needed to obtain

the specified output power. V

equation (4) and I

(4)

(5)

To determine the maximum supply voltage, the following

conditions must be considered. Add the dropout voltage to

the peak output swing V

rent of I

unloaded voltage which is usually about 15% higher. The

supply voltage will also rise 10% during high line conditions.

Therefore the maximum supply voltage is obtained from the

following equation:

Max Supplies

For 25W of output power into an 8

Ω load, the required V

O-

PEAK

ing V

(5). At this point it is a good idea to check the Power Output

vs Supply Voltage to ensure that the required output power is

obtainable from the device while maintaining low THD+N. In

addition, the designer should verify that with the required

power supply voltage and load impedance, that the required

heatsink value

θ

constraints. Once the heatsink issues have been addressed,

the required gain can be determined from equation (6).

(6)

From equation (6), the minimum A

By selecting a gain of 21, and with a feedback resistor, R

20 k

Ω, the value of R

R

(7)

Thus with R

Since the desired input impedance was 47 k

Ω, a value of 47

k

Ω was selected for R

the bandwidth requirements which must be stated as a pair

of −3 dB frequency points. Five times away from a −3 dB

DS100835-9

FIGURE 5. Level Shift Circuit

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