SSD1812 datasheet(14/28 Pages) ETC

14 / 28 page

SSD1812

REV 1.2

12/99

SOLOMON

M/S

This pin is master/slave mode selection input. When this pin is pulled

high, master mode is selected and CL, M, MSTAT and DOF will be output

to slave devices. When pulled low, slave mode is selected. CL, M, DOF are

required to be input from master device while MSTAT is high impedance.

This pin is the frame signal input/output. In master mode, the pin supplies

frame signal to slave devices while in slave mode, the pin receives frame

signal from the master device.

MSTAT

This pin is used together with M in master operation for static drive out-

put. It becomes high impedance in slave mode operation.

This pin is the display clock input/output. In master mode, the pin sup-

plies display clock signal to slave devices while in slave mode, the pin

receives display clock signal from the master device.

DOF

This pin is LCD blanking control input/output. In master mode, the pin

supplies on/off signal to slave devices. In slave mode, the pin receives on/

off signal from the master device.

CLS

This pin is a internal clock enable input pin. When this pin is high, the

internal clock is enabled. The internal clock will be disabled when it is low,

an external clock should be input to CL pin.

RES

This pin is reset signal input. When the pin is low, initialization of the chip

is executed.

P/S

This pin is serial/parallel interface select input. When P/S is high, parallel

mode is selected and when P/S is low, serial mode is selected. In serial

mode, only write operation is allowed.

CS1, CS2

These pin are chip select inputs. The chip is enabled for data operation

only when CS1 is low and CS2 is high.

C68/80

This pin is microprocessor interface select input. When the pin is high,

6800 series interface is selected and when the pin is low, 8080 series inter-

face is selected.

D0-D7

These pins are 8-bit bi-directional data bus to be connected to the micro-

processor’s data bus. When serial mode is selected, D7 is the serial data

input SDA and D6 is the serial clock input SCK.

D/C

This pin is control/display data input control flag. When the pin is high,

the data on D0-D7 is display data. When the pin is low, the data on D0-D7 is

control data.

R/W(WR)

This pin is microprocessor interface signal. When interfacing to an 6800-

series microprocessor, the signal indicates read mode when high and write

mode when low. When interfacing to an 8080-microprocessor, a data write

operation is initiated when R/W(WR) is low and the chip is selected.

E(RD)

This pin is microprocessor interface signal. When interfacing to an 6800-

series microprocessor, a data operation is initiated when E(RD) is high and

the chip is selected. When interfacing to an 8080-microprocessor, a data

read operation is initiated when E(RD) is low and the chip is selected.

VDD

Power supply pin.

VSS

Ground.

VSS1

Reference voltage input for internal DC-DC converter. The voltage of

generated VEE equals to the multiple factor (2X, 3X or 4X) times the pro-

tential different between this pin, VSS1, and VDD. All generated voltage is

referenced toVDD.

Note: voltage at this input pin must less than or equal to VSS.

VEE

This is the most negative voltage supply pin of the chip. It can be sup-

plied externally or generated by the internal DC-DC converter.

When using internal DC-DC converter as generator, voltage at this pin

is for internal reference only. It CANNOT be used for driving external cir-

cuitries.

C3N, C1P, C1N, C2P and C2N

When internal DC-DC voltage converter is used, external capacitor(s)

is/are connected among these pins.

VL6

This pin is the most negative LCD driving voltage. It can be supplied

externally or generated by the internal regulator.

This pin is an input of the internal voltage regulator. When internal regu-

lator is used to generate VL6, external resistors are connected between

VDD and VF, and VF and VL6, respectively (see application circuit).

VFS

This pin is an input to provide an external voltage reference for the

internal voltage regulator. It is only enabled in External Input chip options.

IRS

This pin is an input pin to enable the internal resistors network for the

voltage regulator when IRS is high. When it is low, the external resistors

R1/R2 should be connected to VL6 and VF.

HPM

This pin is an input pin to enable the high power current mode when it is

low. The contrast curves in High Power Mode will be different to Normal

Mode. Details of the High Power Mode Contrast curve is TBD.

VL2, VL3, VL4 and VL5 (Voltages referenced to VDD)

LCD driving voltages. They can be supplied externally or generated by

the internal smart bias divider. They have the following relationship:

VDD > VL2 > VL3 > VL4 > VL5 > VL6

ROW0 - ROW63

These pins provide the row driving signal COM0 - COM53 to the LCD

panel. See Table.1 about the COM signal mapping in different multiplex

ratio N.

ICONS

This pin is the special icons line.

SEG0 - SEG131

These pins provide the LCD column driving signal. Their voltage level is

VDD during sleep mode and standby mode.

1:6 bias

1:8 bias

VL2

1/6*VL6

1/8*VL6

VL3

2/6*VL6

2/8*VL6

VL4

4/6*VL6

6/8*VL6

VL5

5/6*VL6

7/8*VL6

PIN DESCRIPTIONS

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