TAS5110

SLES028A – MAY 2002 – REVISED SEPTEMBER 2002

7

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functional description

PWM H-bridge state control

The digital interface control signals consists of PWM_AP, PWM_AM, PWM_BP, and PWM_BM. These signals

are a complementary differential signal format for the A-side half-bridge and the B-side half-bridge.

bootstrapped gate drive

The TAS5110 includes two dedicated bootstrapped power supplies. A bootstrap capacitor is connected

between the individual bootstrap pin and the associated output. For example, a capacitor is connected between

the BOOTSTRAPA pin and OUTPUTA pin, and another capacitor is connected between the BOOTSTRAPB

pin and the OUTPUTB pin. The bootstrap power supply minimizes the number of high voltage power supply

levels externally supplied to the system while providing a low-noise supply level for driving the high-side

N-channel DMOS transistors.

low-dropout voltage regulator

Two on-chip low-dropout voltage regulators (LDO) are provided to minimize the number of external power

supplies needed for the system. These voltage regulators are for internal circuits only and cannot be used for

external circuitry. Each LDO is dedicated to a half-bridge and its gate driver. An LDO output capacitor is

connected between the individual LDO output pin and the associated output return. For example, a capacitor

is connected between the LDROUTA pin and PVSS pin, and another capacitor is connected between the

LDROUTB pin and PVSS pin.

high-current H-bridge output stage

The positive outputs of the H-bridge are the two OUTPUTA pins. The negative outputs of the H-bridge are the

two OUTPUTB pins. The logic for the input command to H-bridge outputs is described in the H-bridge output

mapping section below. When the TAS5110 is in the normal mode, as seen in the H-bridge output mapping

tables, the outputs are decoded from the inputs. However, the TAS5110 is immediately shut down if any of the

following error conditions occur: over-current, over-temperature, low regulator output voltage, or an illegal PWM

input state is applied. For these conditions, the outputs are set to the appropriate disabled state as specified

in the H-bridge output mapping section, and the SHUTDOWN pin is set low.

H-bridge output mapping

The A-side half-bridge output is designed to the following truth table:

INPUTS

OUTPUTS

DESCRIPTION

RESET

PWDN

PWM_AP

PWM_AM

SHUTDOWN

OUTPUTA

DESCRIPTION

X

X

X

X

0

0 or Hi-Z†

Shutdown

X

0

X

X

1

Hi-Z

Powerdown

0

1

X

X

1

0

Reset

1

1

0

0

0

0

Shutdown

1

1

0

1

1

0

Normal

1

1

1

0

1

1

Normal

1

1

1

1

0

0

Shutdown

† Output is 0 for low voltage, over temperature, and illegal input. Hi-Z is for over current.