LVDS Interface

DCLK(A,B), DVALID(A,B), DIN(A,B)[15:0]

DLPC910

DOUT(A,B)[15:0]

RESET_MODE(1:0)

SCP BUS(3:0)

Power Management

OSC

50 MHz

CTRL_RSTZ

JTAG(3:0)

DLPR910

PGM(4:0)

Illumination

Driver

Illumination

Sensor

I2C

Row and Block Signals

ROWMD(1:0), ROWAD(10:0), BLKMD(1:0), BLKAD(3:0), RST2BLKZ

Control Signals

COMP_DATA, NS_FLIP, WDT_ENBLZ, PWR_FLOAT

Status Signals

RST_ACTIVE, INIT_ACTIVE, ECP2_FINISHED

VLED0

VLED1

DLP6500

APPS

FPGA

USER

Interface

Connectivity

USB

Ethernet

Volatile

And

Non-Volatile

Storage

DCLKOUT(A,B)

SCTRL(A,B)

RESET_ADDR(3:0)

RESETZ

RESET_SEL(1:0)

RESET_STRB

RESET_OEZ

RESET_IRQZ

11

DLPR910

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DLPS065B – SEPTEMBER 2015 – REVISED NOVEMBER 2016

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Typical Application (continued)

Figure 4. Typical High Speed DLP6500 Application Schematic

8.2.1 Design Requirements

The DLPR910 is part of a multi-chipset solution, and it is required to be coupled with the DLPC910 for reliable

operation of the DLP9000X DMD or the DLP6500 family of DMDs. For more information, refer to the DLPC910

datasheet listed in Related Documentation.

9 Power Supply Recommendations

The DLPR910 uses two power supply rails as shown in Table 1.

Table 1. DLPR910 Power Supply Rails

SUPPLY

POWER PINS

COMMENTS

1.8 V

decoupling capacitor to GND.

3.3 V

µF decoupling capacitor to GND.

10 Layout

10.1 Layout Guidelines

The DLPR910 is part of a multi-chipset solution, and it is required to be coupled with the DLPC910 for reliable

operation of the DLP9000X DMD or the DLP6500 family of DMDs. Refer to the DLPC910 datasheet listed in

Related Documentation for a layout example for this multi-chipset solution.