AD9363ABCZ datasheet(18/32 Pages) AD

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AD9363

Data Sheet

Rev. D | Page 18 of 32

Pin No.

Type1

Mnemonic

Description

I/O

P0_D10/TX_D5_N

Digital Data Port 0, Data Bit 10/Transmit Differential Input Bus, Data Bit 5. This is a

dual function pin. As P0_D10, it functions as part of the 12-bit bidirectional parallel

CMOS level Data Port 0. Alternatively, as TX_D5_N, it functions as part of the LVDS 6-

bit Tx differential input bus with internal LVDS termination.

F10, G10

FB_CLK_P, FB_CLK_N

Feedback Clock Inputs. These pins receive the FB_CLK signal that clocks in Tx data. In

CMOS mode, use FB_CLK_P as the input and tie FB_CLK_N to ground.

F12

VDDD1P3_DIG

1.3 V Digital Supply Input.

RX_VCO_LDO_OUT

Receive VCO LDO Output. Connect to G3 and to a 1 μF bypass capacitor in series

with a 1 Ω resistor to ground.

VDDA1P1_RX_VCO

Receive VCO Supply Input. Connect to G2.

EN_AGC

Manual Control Input for Automatic Gain Control (AGC).

ENABLE

Control Input. This pin moves the device through various operational states.

G7, G8

RX_FRAME_N,

RX_FRAME_P

Receive Digital Data Framing Outputs. These pins transmit the RX_FRAME signal that

indicates whether the Rx output data is valid. In CMOS mode, use RX_FRAME_P as

the output and leave RX_FRAME_N unconnected.

G9, H9

TX_FRAME_P,

TX_FRAME_N

Transmit Digital Data Framing Inputs. These pins receive the TX_FRAME signal that

indicates when Tx data is valid. In CMOS mode, use TX_FRAME_P as the input and tie

TX_FRAME_N to ground.

G11, H11

DATA_CLK_P,

DATA_CLK_N

Receive Data Clock Outputs. These pins transmit the DATA_CLK signal that the BBP

uses to clock the Rx data. In CMOS mode, use DATA_CLK_P as the output and leave

DATA_CLK_N unconnected.

H1, J1

RX1B_P, RX1B_N

Receive Channel 1 Differential B Inputs. Alternatively, use each pin as a single-ended

input. Unused pins must be tied to ground.

TXNRX

Enable State Machine Control Signal. This pin controls the data port bus direction. A

logic low selects the Rx direction; a logic high selects the Tx direction.

I/O

P1_D11/RX_D5_P

Digital Data Port P1, Data Bit 11/Receive Differential Output Bus, Data Bit 5. This is a

dual function pin. As P1_D11, it functions as part of the 12-bit bidirectional parallel

CMOS level Data Port 1. Alternatively, as RX_D5_P, it functions as part of the LVDS 6-

bit Rx differential output bus with internal LVDS termination.

H12

VDD_INTERFACE

1.2 V to 2.5 V Supply for Digital I/O Pins (1.8 V to 2.5 V in LVDS Mode).

VDDA1P3_RX_SYNTH

Receiver Synthesizer 1.3 V Supply Input.

SPI_DI

SPI Serial Data Input.

SPI_CLK

SPI Clock Input.

CLK_OUT

Output Clock. This pin can be configured to output either a buffered version of the

external input clock (the digital controlled crystal oscillator (DCXO)) or a divided-

down version of the internal ADC sample clock (ADC_CLK).

I/O

P1_D10/RX_D5_N

Digital Data Port 1, Data Bit 10/Receive Differential Output Bus, Data Bit 5. This is a

dual function pin. As P1_D10, it functions as part of the 12-bit bidirectional parallel

CMOS level Data Port 1. Alternatively, as RX_D5_N, it functions as part of the LVDS 6-

bit Rx differential output bus with internal LVDS termination.

I/O

P1_D9/RX_D4_P

Digital Data Port 1, Data Bit 9/Receive Differential Output Bus, Data Bit 4. This is a

dual function pin. As P1_D9, it functions as part of the 12-bit bidirectional parallel

CMOS level Data Port 1. Alternatively, as RX_D4_P, it functions as part of the LVDS 6-

bit Rx differential output bus with internal LVDS termination.

I/O

P1_D7/RX_D3_P

Digital Data Port 1, Data Bit 7/Receive Differential Output Bus, Data Bit 3. This is a

dual function pin. As P1_D7, it functions as part of the 12-bit bidirectional parallel

CMOS level Data Port 1. Alternatively, as RX_D3_P, it functions as part of the LVDS 6-

bit Rx differential output bus with internal LVDS termination.

J10

I/O

P1_D5/RX_D2_P

Digital Data Port 1, Data Bit 5/Receive Differential Output Bus, Data Bit 2. This is a

dual function pin. As P1_D5, it functions as part of the 12-bit bidirectional parallel

CMOS level Data Port 1. Alternatively, as RX_D2_P, it functions as part of the LVDS 6-

bit Rx differential output bus with internal LVDS termination.

J11

I/O

P1_D3/RX_D1_P

Digital Data Port 1, Data Bit 3/Receive Differential Output Bus, Data Bit 1. This is a

dual function pin. As P1_D3, it functions as part of the 12-bit bidirectional parallel

CMOS level Data Port 1. Alternatively, as RX_D1_P, it functions as part of the LVDS 6-

bit Rx differential output bus with internal LVDS termination.

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