AD9363ABCZ datasheet(29/32 Pages) AD

29 / 32 page

Data Sheet

AD9363

Rev. D | Page 29 of 32

BB PLL

The AD9363 also contains a baseband PLL (BB PLL) synthesizer

that generates all baseband related clock signals. These signals

include the ADC and DAC sampling clocks, the DATA_CLK signal

(see the Digital Data Interface section), and all data framing

signals. The BB PLL is programmed from 700 MHz to 1400 MHz

based on the data rate and sample rate requirements of the system.

DIGITAL DATA INTERFACE

The AD9363 data interface uses parallel data ports (P0 and P1)

to transfer data between the device and the BBP. The data ports

can be configured in either single-ended CMOS format or dif-

ferential LVDS format. Both formats can be configured in multiple

arrangements to match system requirements for data ordering

and data port connections. These arrangements include single

port data bus, dual port data bus, single data rate, double data

rate, and various combinations of data ordering to transmit data

from different channels across the bus at appropriate times.

Bus transfers are controlled using simple hardware handshake

signaling. The two ports can be operated in either bidirectional

(TDD) mode or in full duplex (FDD) mode, where half the bits

are used for transmitting data and half are used for receiving

data. The interface can also be configured to use only one of the

data ports for applications that do not require high data rates

and require fewer interface pins.

DATA_CLK Signal

The AD9363 outputs the DATA_CLK signal that the BBP uses

to sample receiver data. The signal is synchronized with the

receiver data such that data transitions occur out of phase with

DATA_CLK. The DATA_CLK can be set to a rate that provides

single data rate (SDR) timing, where data is sampled on each rising

clock edge, or it can be set to provide double data rate (DDR)

timing, where data is captured on both rising and falling clock

edges. SDR or DDR timing applies to operation using either a

single port or both ports.

FB_CLK Signal

For transmit data, the interface uses the FB_CLK signal as the

timing reference. The FB_CLK signal allows source synchro-

nous timing with rising edge capture for burst control signals

and either rising edge capture (SDR mode) or both edge capture

(DDR mode) for transmit signal bursts. The FB_CLK signal

must have the same frequency and duty cycle as DATA_CLK.

RX_FRAME and TX_FRAME Signals

The device generates an RX_FRAME output signal whenever

the receiver outputs valid data. This signal has two modes: level

mode (the RX_FRAME signal stays high as long as the data is

valid) and pulse mode (the RX_FRAME signal pulses with a 50%

duty cycle). Similarly, the BBP must provide a TX_FRAME

signal that indicates the beginning of a valid data transmission

with a rising edge. Like the RX_FRAME signal, the TX_FRAME

signal stays high throughout the burst or it pulses with a 50% duty

cycle.

ENABLE STATE MACHINE

The AD9363 transceiver includes an ENSM that allows real-

time control over the current state of the device. The device can

be placed in several different states during normal operation,

including

•

Wait—power save, synthesizers disabled

•

Sleep—wait with all clocks and the BB PLL disabled

•

Tx—Tx signal chain enabled

•

Rx—Rx signal chain enabled

•

FDD—Tx and Rx signal chains enabled

•

Alert—synthesizers enabled

The ENSM has two control modes: SPI control and pin control.

SPI Control Mode

In SPI control mode, the ENSM is controlled asynchronously by

writing to SPI registers to advance the current state to the next

state. SPI control is considered asynchronous to the DATA_CLK

signal because the SPI clock can be derived from a different

clock reference and can still function properly. The SPI control

ENSM mode is recommended when real-time control of the

synthesizers is not necessary. SPI control can be used for real-

time control as long as the BBP can perform timed SPI writes

accurately.

Pin Control Mode

In pin control mode, the enable functions of the ENABLE pin

and the TXNRX pin allow real-time control of the current state.

The ENSM allows TDD or FDD operation, depending on the

configuration of the corresponding SPI register. The ENABLE

and TXNRX pin control mode is recommended if the BBP has

extra control outputs that can be controlled in real time, allow-

ing a simple 2-wire interface to control the state of the device.

To advance the current state of the ENSM to the next state,

drive the enable function of the ENABLE pin by either a pulse

(edge detected internally) or a level.

When a pulse is used, it must have a minimum pulse width of

one cycle of the FB_CLK signal. In level mode, the ENABLE

and TXNRX pins are also edge detected by the AD9363 and

must meet the same minimum pulse width requirement of one

cycle of the FB_CLK signal.

In FDD mode, the ENABLE and TXNRX pins can be remapped

to serve as real-time Rx and Tx data transfer control signals. In

this mode, the ENABLE pin assumes the receive on (RXON)

function (controls when the Rx path is enabled and disabled), and

the TXNRX pin assumes the transmit on (TXON) function

(controls when the Tx path is enabled and disabled). The ENSM

must be controlled by SPI writes in this mode while the ENABLE

and TXNRX pins control all data flow. For more information

about RXON and TXON, see the AD9363 reference manual,

available from Integrated Wideband RF Transceiver Design

Resources.

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