11

FIGURE 11. MODE CONTROL WORD

FIGURE 12. MODE 2

NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF

• MASK • STB • RD ÷ OBF •

MASK

• ACK • WR)

FIGURE 13. MODE 2 (BI-DIRECTIONAL)

1

D7 D6 D5 D4 D3 D2 D1 D0

CONTROL WORD

1/0 1/0

1

1/0

PC2-PC0

1 = INPUT

0 = OUTPUT

PORT B

1 = INPUT

0 = OUTPUT

GROUP B MODE

0 = MODE 0

1 = MODE 1

PC7

OBFA

PC6

INTE

PA7-PA0

ACKA

IBFA

PC4

WR

INTE

RD

PC3

PC5

PC2-PC0

1

2

8

STBA

3

I/O

INTRA

tWOB

tAOB

tAK

tAD

tKD

tPH

tPS

tSIB

tST

OBF

WR

INTR

ACK

IBF

STB

PERIPHERAL

BUS

RD

tRIB

DATA FROM

PERIPHERAL TO 82C55A

DATA FROM

82C55A TO PERIPHERAL

DATA FROM

82C55A TO CPU

DATA FROM

CPU TO 82C55A

82C55A