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ADS5103 Datasheet(PDF) 17 Page - Texas Instruments |
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ADS5103 Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 23 page ![]() ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 17 www.ti.com PRINCIPLES OF OPERATION 100 k Ω BG 1 µF AVDD Figure 30. BG Reference Configuration For systems that require more absolute accuracy or lower temperature coefficient drift than provided by the internal VREF, an external voltage reference can be applied to the VREFB and VREFT inputs. To use external reference, connect the PDREF pin to a logic high and this internally disconnects the VREF from the ADC. In this mode it is also necessary to connect the BG and REFT pins together on the PWB. It is recommended to use the input levels of VREFB = 0.75 V and VREFB = 1.25 V to achieve optimum ADC performance. It is also recommended to apply a common-mode voltage to the input of 1 V. clock input The clock input is designed for 1.8 V or 3.3 V CMOS logic levels (depends on DRVDD) and it is recommended to use standard CMOS logic levels as inputs. The logic threshold internally is set to DRVDD/2 or nominally 1.65 V. Since both edges of the clock are used in the switch capacitor architecture, it is important to provide a clock with (ideally) a 50% duty cycle. The performance variation with clock duty cycle can be examined from Figures 25, 26, 27 and 28. Clock jitter is also important for performance of the ADC to be maintained. Any clock jitter appears as noise when sampling input frequencies. Clock Jitter reduces the signal to noise ratio (SNR) and is more severe as the input frequency increases. The theoretical SNR limits based on clock jitter can be calculated as follows: Theoretical SNR (clock jitter) (dB) + 20 log 1 2 p F I CLK (jitter) Where: FI = Highest input frequency to the ADC in Hz CLK(jitter) = the amount of jitter on the clock in sec Therefore for a Nyquist frequency input of 32.5 MHz and a design trying to achieve the most available performance from the ADS5102/3, the clock jitter must be less than 3.98 ps rms. In under sampling applications, the same equations apply and clock jitter becomes more critical and may be the limiting factor in system performance. The aperture jitter of the SHA also contributes to overall jitter. For worst case designs, the jitter of clock and aperture can be considered to add in quadrature, i.e. Total Jitter = Square root of ( CLKjitter2 + Aperturejitter 2) The aperture jitter of the ADS5103 is 2 ps rms and at frequencies approaching Nyquist, the total jitter should be accounted for. |
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