ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

18

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PRINCIPLES OF OPERATION

digital outputs

The outputs of the ADS5102/3 are also CMOS and are programmable for either 3.3 V or 1.8 V CMOS logic

results. The output format is offset binary with D0 (LSB) and D9 (MSB). See Table 1 for output coding with a

differential input signal applied. There is a 5.5 clock latency from the sampling to valid data output on D0–D9.

The outputs can be placed into active mode by taking OE low or 3-state by taking OE high. The timing relations

between OE and output bus enable/disable times are shown in the timing diagram (refer to page 7). The

capacitive loading on the digital outputs is very important to achieve best performance. The total load

capacitance is typically made up of two sources, next stage input capacitance and PWB etch run capacitance.

The total capacitance of these two loads should be held to less than 15 pF. If for some reason, this cannot be

met, it is recommended to use logic buffers such as ‘244 placed physically very close to the ADC output. This

isolates the ADC output from the load capacitance and performance specs are achieved. Another technique

is to place a small resistor in series with the outputs. This resistance dampens the current spikes into the

capacitive loads and thus improve ADC performance. The value of this resistor varies with sampling rate but

generally 22

Ω is a good value. Again this depends on the load capacitance.

The digital output of these devices is offset binary and follows the following format.

Table 1. Output Coding

ANALOG INPUT

SIGNAL VOLTAGE

STEP

DIGITAL OUTPUT CODE

ANALOG INPUT

IN +

SIGNAL VOLTAGE

IN –

STEP

MSB

LSB

REFT†

REFB†

1023

1

1

1

1

1

1

1

1

1

1

•

•

•

•

•

•

•

•

•

•

•

•

•

(REFT – REFB) / 2

(REFT – REFB) / 2

512

1

0

0

0

0

0

0

0

0

0

•

•

511

0

1

1

1

1

1

1

1

1

1

•

•

•

•

•

•

•

•

•

•

•

•

•

REFB

REFT

0

0

0

0

0

0

0

0

0

0

0

† Where there is either an internal voltage reference or an external voltage reference applied to the REFT and REFB pins.

driving the analog input

Since many real world signals are single ended and most modern high speed ADC’s employ differential inputs,

it is necessary in many cases to perform single ended to differential conversion prior to the ADC. Also, the ADC

performs optimally if a differential signal is applied to the inputs. In some cases, signal conditioning is required

in the form of the amplification or filtering. The two preferred techniques for driving the ADC input are: 1) With

an active amplifier specifically designed to drive ADC’s; 2) With an RF transformer.

driving the analog input with a differential amplifier

Texas Instruments has developed a family of high quality operational amplifiers that have been designed

specifically for driving the input stage of modern ADC’s. These devices allow for amplification and filtering prior

to the ADC. This stage can be used to set the maximum signal voltage to match the full scale input of the ADC.

The best solution for driving the ADS5102/3 ADC’s is the THS4501 amplifier. Figure 31 shows how to use this

device with a gain of 2. The ADC common mode output voltage can be directly connected to the op amp to

provide the proper levels. The THS4501 provides optimum matching of op amp output to the input of the

ADS5102/3. This configuration provides signal amplification, filtering, and single-ended to differential

conversion. It is recommended to provide de-coupling capacitors of 0.1

µF and 0.001 µF on the CML output.

This filters out any high frequency noise prior the ADC input.