TAS5015

SLES017 – SEPTEMBER 2001

10

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functional description (continued)

Table 4. Hardware Selection of Serial Audio Modes

MODE

MOD2 PIN

MOD1 PIN

MOD0 PIN

SERIAL INTERFACE

SDIN

0

0

0

0

16-bit, MSB first; right justified

1

0

0

1

20-bit, MSB first; right justified

2

0

1

0

24-bit, MSB first; right justified

3

0

1

1

16-bit IIS

4

1

0

0

20-bit IIS

5

1

0

1

24-bit IIS

6

1

1

0

16-bit MSB first, left justified

7

1

1

1

16-bit DSP frame

The following figures illustrate the relationship between the SCLK, LRCLK, and the serial data I/O for the

different interface protocols. Note that there are always 64 SCLKs per LRCLK. The nondata bits are padded

with binary 0s.

MSB first, right-justified (for 16, 20, 24 bits)

X

MSB

LSB

MSB

LSB

SCLK

LRCLK = fs

SDIN

Left Channel

Right Channel

X

Figure 7. MSB First Right Justified

Note the following characteristics of this protocol.

–

Left channel is received when LRCLK is high.

–

Right channel is received when LRCLK is low.

–

SDIN is sampled at the rising edge of SCLK.