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TSL401 Datasheet(PDF) 4 Page - Texas Instruments

Part # TSL401
Description  128 횞 1 LINEAR SENSOR ARRAY
PDF  7 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TSL401 Datasheet(HTML) 4 Page - Texas Instruments

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TSL401
128
× 1 LINEAR SENSOR ARRAY
SOES011 – MARCH 1996
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
electrical characteristics at fclock = 200 kHz, VDD = 5 V, TA = 25°C, λp = 565 nm, tint = 5 ms,
RL = 330 Ω, Ee = 20 µW/cm2 (unless otherwise noted) (see Note 2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog output voltage (white, average over 128 pix-
els)
1.8
2
2.2
V
Analog output voltage (dark, each pixel)
Ee = 0
0
0.15
0.3
V
PRNU
Pixel response nonuniformity
See Note 3
±5%
±7.5%
Linearity of analog output voltage
See Note 4
±0.4%
F.S.
Output noise voltage
See Note 5
1
mVrms
Saturation exposure
136
175
nJ/cm2
Analog output saturation voltage
3
3.5
V
IDD
Supply current
2.5
4
mA
IIH
High-level input current
VI = VDD
1
µA
IIL
Low-level input current
VI = 0
1
µA
Ci
Input capacitance
5
pF
NOTES:
2. Clock duty cycle is assumed to be 50%.
3. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated.
4. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
5. Peak-to-peak noise is the variation of a single-pixel output under constant illumination as observed over a 5-second period.
operating characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tw(H)
Clock pulse duration (high)
50
ns
tw(L)
Clock pulse duration (low)
50
ns
ts
Analog output settling time to
±1%
RL = 330 Ω,
CL = 50 pF
350
ns
tv
Valid time
RL = 330 Ω,
CL = 50 pF,
See Note 2
1/(2 fclock)
s
NOTE 2: Clock duty cycle is assumed to be 50%.
50%
AO
SI
CLK
tv
Pixel 128
Pixel 1
ts
0 V
0 V
5 V
2.5 V
th(SI)
5 V
tsu(SI)
tw
1
2
128
129
ts
Figure 2. Operational Waveforms



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