ES4408 datasheet(3/6 Pages) ETC

3 / 6 page

ESS Technology, Inc.

SAM0241-052101

ES4408 PRODUCT BRIEF

ES4408 PIN DESCRIPTION

Table 1 lists the pin descriptions for the ES4408.

Table 1

ES4408 Pin Descriptions

Name

Number

I/O

Definition

VCC

1, 9, 18, 27, 35, 44,

51, 59, 68, 75, 83,

92, 99, 104, 111,

121, 130, 139, 148,

157, 164, 172, 183,

193, 201

3.65 V ± 150 mv.

LA[21:0]

23:19, 16:10, 7:2,

207:204

Device address output.

VSS

8, 17, 26, 34, 43, 52,

60, 67, 76, 84, 91,

98, 103, 112, 120,

129, 138, 147, 156,

163, 171, 177, 184,

192, 200, 208

Ground.

RESET#

Reset input, active low.

TDMDX

TDM transmit data.

RSEL

ROM Select

TDMDR

TDM receive data.

TDMCLK

TDM clock input.

TDMFS

TDM frame sync.

TDMTSC#

TDM output enable, active low.

TWS

Audio transmit frame sync.

SEL_PLL[2:0]

Select PLL1.

TSD[3:0]

38,37,36,33

Audio transmit serial data port.

MCLK

I/O

Audio master clock for audio DAC.

TBCK

I/O

Audio transmit bit clock.

SPDIF_DOBM

S/PDIF (IEC958) Format Output.

RSD

Audio receive serial data.

RWS

Audio receive frame sync.

RBCK

Audio receive bit clock.

APLLCAP

Analog PLL Capacitor.

XIN

Crystal input.

XOUT

Crystal output.

DMA[11:0]

66:61, 58:53

DRAM address bus.

DCAS#

Column address strobe, active low.

DOE#

Output enable, active low.

DSCK_EN

Clock Enable, active low.

DWE#

DRAM write enable, active low.

DRAS[2:0]#

74:72

Row address strobe, active low.

DB[15:0]

96:93, 90:85, 82:77

I/O

DRAM data bus.

DCS[1:0]#

97,100

SDRAM chip select [1:0], active low.

RSEL

Selection

8-bit ROM

16-bit ROM

SEL_PLL2 SEL_PLL0 Clock Output

2.5 x DCLK

3 x DCLK

3.5 x DCLK

4 x DCLK

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