Philips Semiconductors

Product specification

NE/SE564

Phase-locked loop

1994 Aug 31

5

FUNCTIONAL DESCRIPTION

(Figure 6)

The NE564 is a monolithic phase-locked loop with a post detection

processor. The use of Schottky clamped transistors and optimized

device geometries extends the frequency of operation to greater

than 50MHz.

In addition to the classical PLL applications, the NE564 can be used

as a modulator with a controllable frequency deviation.

The output of the PLL can be written as shown in the following

equation:

(1)

The process of recovering FSK signals involves the conversion of

the PLL output into logic compatible signals. For high data rates, a

considerable amount of carrier will be present at the output of the

PLL due to the wideband nature of the loop filter. To avoid the use

of complicated filters, a comparator with hysteresis or Schmitt trigger

is required. With the conversion gain of the VCO fixed, the output

voltage as given by Equation 1 varies according to the frequency

is necessary that the hysteresis of the Schmitt trigger be capable of

being changed, so that it can be optimized for a particular system.

This is accomplished in the 564 by varying the voltage at Pin 15

which results in a change of the hysteresis of the Schmitt trigger.

For FSK signals, an important factor to be considered is the drift in

the free-running frequency of the VCO itself. If this changes due to

temperature, according to Equation 1 it will lead to a change in the

DC levels of the PLL output, and consequently to errors in the digital

output signal. This is especially true for narrowband signals where

temperature. This effect can be eliminated if the DC or average

value of the signal is retrieved and used as the reference to the

comparator. In this manner, variations in the DC levels of the PLL

output do not affect the FSK output.

VCO Section

Due to its inherent high-frequency performance, an emitter-coupled

oscillator is used in the VCO. In the circuit, shown in the equivalent

schematic, transistors Q21 and Q23 with current sources Q25 - Q26

form the basic oscillator. The approximate free-running frequency of

the oscillator is shown in the following equation:

1

(2)

frequency of the oscillator. As indicated by Equation 2, the

frequency of the oscillator has a negative temperature coefficient

with negative temperature coefficient is introduced to achieve a low

frequency drift with temperature.

Phase Comparator Section

The phase detection processor consists of a doubled-balanced

modulator with a limiter amplifier to improve AM rejection.

Schottky-clamped vertical PNPs are used to obtain TTL level inputs.

which effectively changes the gain of the differential amplifiers. This

can be accomplished by introducing a current at Pin 2.

Post Detection Processor Section

The post detection processor consists of a unity gain

transconductance amplifier and comparator. The amplifier can be

used as a DC retriever for demodulation of FSK signals, and as a

post detection filter for linear FM demodulation. The comparator has

adjustable hysteresis so that phase jitter in the output signal can be

eliminated.

As shown in the equivalent schematic, the DC retriever is formed by

capacitor which is connected at the amplifier output (Pin 14). This

forms an integrator whose output voltage is shown in the following

equation:

(3)

varied so that the output voltage is the DC or average value of the

input signal for use in FSK, or as a post detection filter in linear

demodulation.

loop gain of the comparator. This method of hysteresis control,

which is a DC control, provides symmetric variation around the

nominal value.

Design Formula

The free-running frequency of the VCO is shown by the following

equation:

(4)

1

The loop filter diagram shown is explained by the following equation:

(5)

1

(First Order)

By adding capacitors to Pins 4 and 5, a pole is added to the loop

transfer at

ω =

1

NOTE:

*Refer to Figure 6.