PCF85116 datasheet(11/20 Pages) PHILIPS

11 / 20 page

1997 Apr 02

Philips Semiconductors

Product speciﬁcation

2048

× 8-bit CMOS EEPROM with I2C-bus

interface

PCF85116-3

Note

1. The bus capacitance ranges from 10 to 400 pF (Cb = total capacitance of one bus line in pF).

11 I2C-BUS CHARACTERISTICS

All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and

VIH with an input voltage swing from VSS to VDD.

Notes

1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be

internally provided by a transmitter.

2. Cb = total capacitance of one bus line in pF.

SCL input (pin 6)

VIL

LOW level input voltage

−0.8

+0.3VDD

VIH

HIGH level input voltage

0.7VDD

6.5

ILI

input leakage current

VI =VDD or VSS

−±1

µA

fSCL

clock input frequency

400

kHz

tSP

pulse width of spikes suppressed by ﬁlter

100

input capacitance

VI =VSS

−

7pF

WP input (pin 7)

VIL

LOW level input voltage

−0.8

+0.1VDD

VIH

HIGH level input voltage

0.9VDD

VDD + 0.8

Data retention time

data retention time

Tamb =55 °C20

−

years

SYMBOL

PARAMETER

CONDITIONS

STANDARD MODE

FAST MODE

UNIT

MIN.

MAX.

MIN.

MAX.

fSCL

clock frequency

100

400

kHz

tBUF

time the bus must be free before

new transmission can start

4.7

−

1.3

−µs

tHD;STA

START condition hold time after

which ﬁrst clock pulse is generated

4.0

−

0.6

−µs

tLOW

LOW level clock period

4.7

−

1.3

−µs

tHIGH

HIGH level clock period

4.0

−

0.6

−µs

tSU; STA

set-up time for START condition

repeated start

4.7

−

0.6

−µs

tHD; DAT

data hold time

for CBUS compatible masters

−−

−µs

for I2C-bus devices

note 1

−

tSU; DAT

data set-up time

250

−

100

−

SDA and SCL rise time

−

1000

20 + 0.1Cb(2) 300

SDA and SCL fall time

−

300

20 + 0.1Cb(2) 300

tSU; STO

set-up time for STOP condition

4.0

−

0.6

−µs

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

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