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M48Z128, M48Z128Y, M48Z128V*

READ Mode

The M48Z128/Y/V is in the READ Mode whenever

W (WRITE Enable) is high and E (Chip Enable) is

low. The device architecture allows ripple-through

access of data from eight of 1,048,576 locations in

the static storage array. Thus, the unique address

specified by the 17 address inputs defines which

one of the 131,072 bytes of data is to be accessed.

Valid data will be available at the Data I/O pins

address input signal is stable, providing that the E

and G (Output Enable) access times are also sat-

isfied. If the E and G access times are not met, val-

id data will be available after the later of Chip

state Data I/O signals is controlled by E and G. If

lines will be driven to an indeterminate state until

and G remain low, output data will remain valid for

minate until the next Address Access.

Figure 7. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms

Note: WRITE Enable (W) = High.

Figure 8. Address Controlled, READ Mode AC Waveforms

Note: Chip Enable (E) and Output Enable (G) = Low, WRITE Enable (W) = High.

AI01197

tAVAV

tAVQV

tAXQX

tELQV

tELQX

tEHQZ

tGLQV

tGLQX

tGHQZ

DATA OUT

A0-A16

E

G

DQ0-DQ7

VALID

AI01078

tAVAV

tAVQV

tAXQX

A0-A16

DQ0-DQ7

VALID

DATA VALID