M48Z128V datasheet(11/21 Pages) STMICROELECTRONICS

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M48Z128, M48Z128Y, M48Z128V*

WRITE Mode

The M48Z128/Y/V is in the WRITE Mode whenev-

er W and E are active. The start of a WRITE is ref-

erenced from the latter occurring falling edge of W

or E. A WRITE is terminated by the earlier rising

edge of W or E.

The addresses must be held valid throughout the

cycle. E or W must return high for minimum of

tEHAX from E or tWHAX from W prior to the initiation

of another READ or WRITE cycle. Data-in must be

valid tDVWH prior to the end of WRITE and remain

valid for tWHDX or tEHDX afterward. G should be

kept high during WRITE cycles to avoid bus con-

tention; although, if the output bus has been acti-

vated by a low on E and G, a low on W will disable

the outputs tWLQZ after W falls.

Figure 9. WRITE Enable Controlled, WRITE AC Waveforms

Note: Output Enable (G) = High.

Figure 10. Chip Enable Controlled, WRITE AC Waveforms

Note: Output Enable (G) = High.

AI01198

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A16

DQ0-DQ7

VALID

tAVWH

tAVEL

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

AI01199

tAVAV

tEHAX

tDVEH

A0-A16

DQ0-DQ7

VALID

tAVEH

tAVEL

tAVWL

tELEH

tEHDX

DATA INPUT

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