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M48Z128V Datasheet(PDF) 3 Page - STMicroelectronics

Part # M48Z128V
Description  5.0V OR 3.3V, 1 Mbit (128 Kbit x 8) ZEROPOWER SRAM
PDF  21 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M48Z128V Datasheet(HTML) 3 Page - STMicroelectronics

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M48Z128, M48Z128Y, M48Z128V*
DESCRIPTION
The M48Z128/Y/V ZEROPOWER® RAM is a
128 Kbit x 8 non-volatile static RAM organized
as131,072 words by 8 bits. The device combines
an internal lithium battery, a CMOS SRAM and a
control circuit in a plastic, 32-pin DIP module. This
solution is available in two special packages to
provide a highly integrated battery backed-up
memory solution.
The M48Z128/Y/V is a non-volatile pin and func-
tion equivalent to any JEDEC standard 128K x 8
SRAM. It also easily fits into many ROM, EPROM,
and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed. The 32-pin,
600mil DIP Module houses the M48Z128/Y/V sili-
con with a long life lithium button cell in a single
package.
For surface-mount environments ST provides an
equivalent SMT solution consisting of a 28-pin,
330mil SOIC NVRAM SUPERVISOR (M40Z300/
W) and a 32-pin, (TSOP, 8 x 20mm) 1Mb
LPSRAM. Both 5V and 3V versions are available
(see Table 2, page 5).
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT® housing con-
taining the battery.
The unique design allows the SNAPHAT battery
package to be mounted on top of the SOIC pack-
age after the completion of the surface-mount pro-
cess. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
The SNAPHAT battery package is shipped sepa-
rately in plastic anti-static tubes or in Tape & Reel
form. The part number is “M4Zxx-BR00SH” (see
Table 13, page 15).
Figure 2. Logic Diagram
Table 1. Signal Names
AI01194
17
A0-A16
W
DQ0-DQ7
VCC
M48Z128
M48Z128Y
M48Z128V
G
VSS
8
E
A0-A16
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable Input
G
Output Enable Input
W
WRITE Enable Input
VCC
Supply Voltage
VSS
Ground
NC
Not Connected Internally



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