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 2002 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC1544

PRELIMINARY

Theory Of Operation

The SC1544 provides a simple way to power five seperate

voltage buses while controlling them correctly using the

ACPI control interface (PWR_OK, /SLP_S3 and /SLP_S5).

It requires only a single supply rail (5VSB from the system

silver box) to operate. An internal charge pump generates

the gate voltages required to enable the use of n-channel

.ETs throughout the design. The external .ETs are

operated in two discrete modes:

1) as pass devices where V

2) as linear regulators.

Please refer to the “Gates At A Glance” section on page

8 and the Typical Applications Circuits on page 11 to

determine which .ETs operate in which mode.

Linear Mode: the SC1544 contains a bandgap reference

trimmed for optimal temperature coefficient which is fed

into the inverting input of an error amplifier. The output

voltage of each linear regulator (monitored by the sense

pin for that output) is divided down internally using a

resistor divider and compared to the bandgap voltage.

The error amplifier drives the gate of the appropriate

external .ET to maintain the voltage at the non inverting

input, and hence the output voltage.

Pass Device Mode: when a particular output is enabled

(please refer to the “Power Matrix” section on page 8) in

pass mode (i.e. 5VSB to 5V Dual), the appropriate gate

drive will be driven high to turn the .ET hard on, minimizing

the voltage drop due to I

The sense pins serve two functions:

1) to sense the output voltage for the linear regulators

2) to sense the output voltage for over current protection

Over Current Protection is provided for all dual outputs.

OCP is implemented by utilizing the R

the output current increases, the regulation loop

maintains the output voltage (linear mode only) by turning

on the .ET more and more. Eventually, as the R

limit is reached (pass devices are already operating at

this point) the .ET will be unable to turn on any further

and the output voltage will start to fall. When the output

voltage falls to approximately 50% of nominal, all outputs

are latched off. Toggling the enable pin or cycling 5VSB

will reset the latch.

Applications Information

To prevent false latching due to capacitor inrush currents,

low supply rails or momentary overloads, the current limit

latch has a timer. If V

before the timer “times out”, then the outputs do not

latch.

Reducing Commutation Noise

The slew rate of the linears is slow enough to provide

soft commutation. The non-linear switch outputs (5V and

3.3V Duals) have fast slew rates. It may be necessary to

put a resistor in series with the gate to reduce transients

(3.3V Dual Memory shown):

3.3V

3.3V DUAL MEM

U 1

SC1544-3.3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

G5

3.3VDM

G6

G7

AGP

TYPEDET

PWR_OK

EN

/S3

/S5

USB

P CI

-CAP

+CAP

FC

5VSB

5VD

G1

G2/3

GND

3.3VD

G4

1.8V

G8

R1

10k (typ.)

Q5

IRLR3103

Another possible source of commutation noise occurs at

startup on 3.3V Dual Memory, when the standby .ET, Q6

and the pass-through .ET, Q5 are both off. 3.3V Dual

Memory will charge to 3.3V minus 0.7V (the drop across

the Q5 body diode). When PWR_OK asserts, Q6 turns on

shorting 3.3V to 3.3V Dual Memory, pulling it down locally

momentarily. This should not be an issue as long as there

is sufficient capacitance on 3.3V locally. Another way to

reduce this drop is to place a schottky diode across Q5

with the cathode towards 3.3V Dual Memory so this rail

charges to 3.3V minus 0.4V, thus reducing the drop when

Q5 turns on:

TO PIN 2

3.3V

TO PIN 1

+

C1

Increase bulk capacitance (preferred)

3.3V DUAL MEM

Q5

IRLR3103

D1 (optional)