CN-0269

Circuit Note

Rev. 0 | Page 4 of 12

delay of ADG5208 is 160 ns. So, the 90% settling time of the

ADG5208 is

(

)(

)

ns

21

pF

35

pF

52

160

100

10

ln

–

%)

90

(

=

+

Ω













=

300

||

SETTLE

t

From Equation 1,

Therefore, under this circuit configuration with the ADG5208

and the ADG5236, the total extra time delay due to the digital

circuits is

Actually, this digital delay of 147 ns due to the digital control

circuit and part of the transition delay from multiplexer can be

compensated by delaying the rising edge of the convert signal

with respect to the multiplexer update signal by an amount of

of temperature, power supply voltage, and normal variations

from part to part. The time margin must be enough to account

for the variation and drift. For example, under this configuration

with 147 ns digital delay, switching the multiplexer 100 ns to

available settling time by the same amount.

The optimized timing is shown in Figure 4, but was not

implemented in the actual circuit in order to minimize

complexity.

Figure 4. Optimized Timing of Multichannel Data Acquisition Circuit

MUX CTRL

[0000]

[0001]

TO CH0

SETTLING TO CH1

CONVERSION

ACQUISITION

CNV

STATUS

[CH3:CH0]

VOUT_SW