Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

WM8608 Datasheet(PDF) 18 Page - Wolfson Microelectronics plc

Part # WM8608
Description  5 TO 7.1 CHANNEL PWM CONTROLLER
PDF  54 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8608 Datasheet(HTML) 18 Page - Wolfson Microelectronics plc

Back Button WM8608 Datasheet HTML 14Page - Wolfson Microelectronics plc WM8608 Datasheet HTML 15Page - Wolfson Microelectronics plc WM8608 Datasheet HTML 16Page - Wolfson Microelectronics plc WM8608 Datasheet HTML 17Page - Wolfson Microelectronics plc WM8608 Datasheet HTML 18Page - Wolfson Microelectronics plc WM8608 Datasheet HTML 19Page - Wolfson Microelectronics plc WM8608 Datasheet HTML 20Page - Wolfson Microelectronics plc WM8608 Datasheet HTML 21Page - Wolfson Microelectronics plc WM8608 Datasheet HTML 22Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 18 / 54 page
background image
WM8608
Product Preview
w
PP Rev 1.5 March 2004
18
I
2S MODE
In I
2S mode, the MSB is sampled on the second rising edge of BCLK following a LRCLK transition.
LRCLK is low during the left samples and high during the right samples.
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
DINFRONT
DINSRND
DINC_LFE
DINREAR
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
1 BCLK
1 BCLK
Figure 11 I
2S Mode TIming Diagram
DSP MODE A AND B
In DSP mode, the Front Left (FL) channel MSB is available on either the 1
st (mode B) or 2nd (mode
A) rising edge of BCLK (selectable by LRP) following a rising edge of LRCLK. Right channel data
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
LRCLK
BCK
DINFRONT
Input Word Length (IWL)
1/fs
DINFRONT
LEFT
n
2
1
n-1
LSB
MSB
n
2
1
n-1
DINFRONT
RIGHT
2
1
DINSRND
LEFT
n
n-1
DINREAR
RIGHT
NO VALID DATA
1 BCLK
1 BCLK
Figure 12 DSP Mode A Timing Diagram
LRCLK
BCK
DINFRONT
Input Word Length (IWL)
1/fs
DINFRONT
LEFT
n
2
1
n-1
LSB
MSB
n
2
1
n-1
DINFRONT
RIGHT
2
1
DINSRND
LEFT
n
n-1
DINREAR
RIGHT
NO VALID DATA
1
Figure 13 DSP Mode B Timing Diagram



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com