ZSC31014EAC datasheet(22/58 Pages) IDT

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ZSC31014 Datasheet

January 20, 2016

Note: There are three differences in the ZSC31014 protocol compared with the original I

2C™ protocol:

• Sending a start-stop condition without any transitions on the CLK line (no clock pulses in between) creates

a communication error for the next communication, even if the next start condition is correct and the clock

pulse is applied. An additional start condition must be sent, which results in restoration of proper

communication.

• The restart condition—a falling SDA edge during data transmission when the CLK clock line is still high—

creates the same situation. The next communication fails, and an additional start condition must be sent for

correct communication.

• A falling SDA edge is not allowed between the start condition and the first rising SCL edge. If using an

2C™ address with the first bit 0, SDA must be held low from the start condition through the first bit.

2.3.5. Digital Interface – SPI

SPI is available only as half duplex (read-only from the ZSC31014). SPI cannot be used in the calibration

environment (Command Mode) because it does not support receiving commands. SPI speeds of up to 200kHz

can be supported in 1MHz Mode, and up to 800kHz can be supported in 4MHz Mode. See Figure 2.5 for the SPI

timing diagram and Table 2.8 for definitions of the parameters shown in the timing diagram.

Table 2.8

SPI Parameters

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

SCLK clock frequency (4MHz clock)

fSCL

800

kHz

SCLK clock frequency (1MHz clock)

fSCL

200

kHz

SS drop to first clock edge

tHDSS

2.5

µs

Minimum SCLK clock low width

tLOW

0.6

µs

Minimum SCLK clock high width

tHIGH

0.6

µs

Clock edge to data transition

tCLKD

0.1

µs

Rise of SS relative to last clock edge

tSUSS

0.1

µs

Bus free time between rise and fall of SS

tBUS

µs

Combined low and high widths must equal or exceed minimum SCLK period.

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