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WM8737 Datasheet(PDF) 32 Page - Wolfson Microelectronics plc |
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WM8737 Datasheet(HTML) 32 Page - Wolfson Microelectronics plc |
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32 / 38 page ![]() WM8737L Preliminary Technical Data w AI Rev 3.0 May 2004 32 Standby mode 1 is achieved by powering down everything except the VMID source and gives a very low power sleep mode. Wake-up may require a few milliseconds to ensure that the VREF voltage has stabilized. Standby mode 2 is achieved by not powering down VMID and VREF. The WM8737L can awaken instantly from standby mode 2 because VREF is already stable. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 8 VMID 0 VMID (necessary for all other functions) 7 VREF 0 VREF (necessary for all other functions) 6 AI 0 Audio Interface 5 PGL 0 PGA Left 4 PGR 0 PGA Right 3 ADL 0 ADC Left 2 ADR 0 ADC Right R6 (06h) Power Manageme nt 1:0 MICBIAS 00 see “Microphone Bias” section R2 (02h) 4 LMBE 0 Mic Boost Left (see “Input Signal Path”) R3 (03h) 4 RMBE 0 Mic Boost Right (see “Input Signal Path”) Notes: All control bits are 0=OFF, 1=ON Table 20 Power Management REGISTER MAP REGISTER ADDRESS (BIT 15 – 9) REMARKS BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 R0 (00h) 0000000 Left PGA LVU LINVOL [7:0] R1 (01h) 0000001 Right PGA RVU RINVOL [7:0] R2 (02h) 0000010 Audio Path L LINSEL LMICBOOST LMBE LMZC LPZC LZCTO[1:0] R3 (03h) 0000011 Audio Path R RINSEL RMICBOOST RMBE RMZC RPZC RZCTO[1:0] R4 (04h) 0001011 3D Enhance 0 DIV2 3DLC 3DUC 3DDEPTH 3DE R5 (05h) 0000101 ADC Control MONOMIX POLARITY HPOR 0 LP MONOUT ADC HPD R6 (06h) 0000110 Power Mgmt VMID VREF AI PGL PGR ADL ADR MICBIAS R7 (07h) 0000111 Audio Format 0 SDODIS MS 0 LRP WL FORMAT R8 (08h) 0001000 Clocking 0 AUTO DETECT CLK DIV2 SR (Sample Rate Selection) USB Mode R9 (09h) 0001001 Mic Preamp Control 0 0 0 0 0 RBYPEN LBYPEN MBCTRL[1:0] R10 (0Ah) 0001010 Misc. biases control 0 0 0 0 0 VMIDSEL [1:0] LINPUT1 dc BIAS ENABLE RINPUT1 dc BIAS ENABLE R11 (0Bh) 0000100 Noise Gate 0 0 0 0 NGTH (Threshold) 0 NGAT R12 (0Ch) 0001100 ALC1 ALCSEL MAXGAIN ALCL (Target Level) R13 (0Dh) 0001101 ALC2 Reserved (must write zeros) 0 ALCZCE HLD (Hold Time) R14 (0Eh) 0001110 ALC3 0 DCY (Decay Time) ATK (Attack Time) R15 (0Fh) 0001111 Reset RESET (writing 000000000 to this register resets all registers to their default state) Table 21 Control Register Map |
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