X1226 datasheet(13/24 Pages) XICOR

13 / 24 page

X1226

REV 1.1.24 1/13/03

Characteristics subject to change without notice.

13 of 24

www.xicor.com

Random Read

Random read operations allow the master to access

any location in the X1226. Prior to issuing the Slave

Address Byte with the R/W bit set to zero, the master

must ﬁrst perform a “dummy” write operation.

The master issues the start condition and the slave

address byte, receives an acknowledge, then issues

the word address bytes. After acknowledging receipt of

each word address byte, the master immediately

issues another start condition and the slave address

byte with the R/W bit set to one. This is followed by an

acknowledge from the device and then by the eight bit

data word. The master terminates the read operation

by not responding with an acknowledge and then issu-

ing a stop condition. Refer to Figure 12 for the address,

acknowledge, and data transfer sequence.

In a similar operation called “Set Current Address,” the

device sets the address if a stop is issued instead of

the second start shown in Figure 12. The X1226 then

goes into standby mode after the stop and all bus

activity will be ignored until a start is detected. This

operation loads the new address into the address

counter. The next Current Address Read operation will

read from the newly loaded address. This operation

could be useful if the master knows the next address it

needs to read, but is not ready for the data.

Sequential Read

Sequential reads can be initiated as either a current

address read or random address read. The ﬁrst data

byte is transmitted as with the other modes; however,

the master now responds with an acknowledge, indi-

cating it requires additional data. The device continues

to output data for each acknowledge received. The mas-

ter terminates the read operation by not responding with

an acknowledge and then issuing a stop condition.

The data output is sequential, with the data from

address n followed by the data from address n + 1. The

address counter for read operations increments

through all page and column addresses, allowing the

entire memory contents to be serially read during one

operation. At the end of the address space the counter

“rolls over” to the start of the address space and the

X1226 continues to output data for each acknowledge

received. Refer to Figure 13 for the acknowledge and

data transfer sequence.

Figure 12. Random Address Read Sequence

Slave

Address

Word

Address 1

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

Word

Address 0

00 0 0 0 0 0

Figure 13. Sequential Read Sequence

Data

(2)

Slave

Address

Data

(n)

SDA Bus

Signals from

the Slave

Signals from

the Master

Data

(n-1)

(n is any integer greater than 1)

Data

(1)

X1226 Datasheet(PDF) 13 Page - Xicor Inc.

X1226 Datasheet(HTML) 13 Page - Xicor Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL