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DAC38RF80 Datasheet(PDF) 21 Page - Texas Instruments

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Part # DAC38RF80
Description  Dual- or Single-Channel, Single-Ended or Differential-Output, 14-bit, 9-GSPS, RF-Sampling DAC with JESD204B Interface and On-Chip PLL
PDF  155 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DAC38RF80 Datasheet(HTML) 21 Page - Texas Instruments

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DAC38RF80, DAC38RF83, DAC38RF84
DAC38RF85, DAC38RF90, DAC38RF93
www.ti.com
SLASEA3A – DECEMBER 2016 – REVISED FEBRUARY 2017
DAC38RF83 DAC38RF93
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
7.8 Timing Requirements
MIN
NOM
MAX
UNIT
DIGITAL INPUT TIMING SPECIFICATIONS
TIMING: SYSREF+/-
ts(SYSREF)
Setup time, SYSREF+/- valid to rising
edge of DACCLK+/-
SYSREF Capture assist disabled
50
ps
th(SYSREF)
Hold time, SYSREF+/- valid after rising
edge of DACCLK+/-
SYSREF Capture assist disabled
50
ps
TIMING: SERIAL PORT
ts(/SDEN)
Setup time, SDEN to rising edge of SCLK
20
ns
ts(SDIO)
Setup time, SDIO valid to rising edge of SCLK
10
ns
th(SDIO)
Hold time, SDIO valid after rising edge of SCLK
5
ns
t(SCLK)
Period of SCLK
temperature sensor read
1
µs
All other registers
100
ns
td(Data)
Data output delay after falling edge of SCLK
25
ns
tRESET
Minimum RESET pulse width
25
ns
ANALOG OUTPUT
ts(DAC)
Output settling time to 0.1%
1
ns
tr
Output rise time 10% to 90%
50
ns
tf
Output fall time 90% to 10%
50
ns
LATENCY
RX SerDes AnalogDelay
250
ps
DAC wake-up time
IOUT current settling to 1% of IOUTFS
from deep sleep
90
µs
DAC sleep time
IOUT current settling to less than 1% of
IOUTFS in deep sleep
90
µs



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