DAC38RF80 datasheet(49/155 Pages) TI1

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DAC38RF80, DAC38RF83, DAC38RF84

DAC38RF85, DAC38RF90, DAC38RF93

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SLASEA3A – DECEMBER 2016 – REVISED FEBRUARY 2017

DAC38RF83 DAC38RF93

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When field SYSR_STATUS_ENA is high the device records the phase associated with each SYSREF event for

use in characterizing the SYSREF capture timing and selecting an appropriate phase tolerance window. The

phase data is available in two forms. First, each of the four phases has a corresponding “sticky” alarm flag

indicating which phases have been observed since the last time the register was cleared. In addition, the device

also accumulates statistics on the relative number of occurrences of each phase spanning multiple SYSREF

events using saturating 8-bit counters. These accumulated real-time SYSREF statistics allow us to account for

time-varying effects during characterization such as potential timing differences between the 1st and Nth edges

in a “gapped” SYSREF pulse train. The counters are fields PHASE1_CNT and PHASE2_CNT in register

SYSREF12_CNT (8.5.10), PHASE3_CNT and PHASE4_CNT in register SYSREF34_CNT (8.5.11), and

ALIGN_TO_R1_CNT and ALIGN_TO_R3_CNT in register SYSREF_ALIGN_R (8.5.9).

The accumulated SYSREF statistics can be cleared by writing ‘1’ to SYSR_ALIGN_SYNC. This sync signal

affects only the SYSREF statistics monitors and does not cause a sync of any other portions of the design.

Before collecting phase statistics, the user must first enable the SYSREF status monitoring logic by setting the

SYSR_STATUS_ENA

bit.

The

user

must

then

generate

repeating

SYSREF

input

before

using

SYSR_ALIGN_SYNC to clear the statistic counters. This is necessary to flush invalid data out of the status

pipeline.

The “sticky” alarm flags indicating which of the four phases have been observed since the last

SYSR_ALIGN_SYNC write of ‘1’ are fields ALM_SYSRPHASE1 to ALM_SYSRPHASE4 and are contained in the

ALM_SYSREF_DET register (8.5.6).

8.3.11 JESD204B Subclass 0 support

Some functionality has been implemented to support Subclass 0 operation. Note that programming the

SUBCLASSV configuration parameter has no functional impact on the logic. The value programmed for

SUBCLASSV is only used in the initial lane alignment (ILA) sequence. The following configuration parameters

are used to support Subclass 0 operation:

•

Field SYSREF_MODE in register JESD_SYSR_MODE (8.5.56) = 0

•

Field DISABLE_ERR_RPT in register JESD_ERR_OUT (8.5.53) = 1

•

Field MIN_LATENCY_ENA in register JESD_MATCH (8.5.50) = 1

8.3.12 SerDes Test Modes through Serial Programming

The DAC38RFxx supports a number of basic pattern generation and verification of SerDes via the serial

interface. Three pseudo random bit stream (PRBS) sequences are available, along with an alternating 0/1

pattern and a 20-bit user-defined sequence. The 27 - 1, 231 - 1 or 223 – 1 sequences implemented can often be

found programmed into standard test equipment, such as a Bit Error Rate Tester (BERT). Pattern generation and

verification selection is via field TESTPATT in register SRDS_CFG1 (8.5.86), as shown in Table 23.

Table 23. SerDes Test Pattern Selection

TESTPATT

EFFECT

000

Test mode disabled.

001

Alternating 0/1 Pattern. An alternating 0/1 pattern with a period of 2 UI.

010

Verify 27 - 1 PRBS. Uses a 7-bit LFSR with feedback polynomial x7 + x6 + 1.

011

Verify 223 - 1 PRBS. Uses an ITU O.150 conformant 23-bit LFSR with feedback polynomial x23 + x18 + 1.

100

Verify 231 - 1 PRBS. Uses an ITU O.150 conformant 31-bit LFSR with feedback polynomial x31 + x28 + 1.

101

User-defined 20-bit pattern. Uses the USR PATT IEEE1500 Tuning instruction field to specify the pattern. The default

value is 0x66666.

11x

Reserved.

Pattern verification compares the output of the serial to parallel converter with an expected pattern. When there

is a mismatch, the TESTFAIL bit is driven high, which can be programmed to come out the ALARM terminal by

setting field DTEST in register DTEST (8.5.76) to “0011”.

DAC38RF80 Datasheet(PDF) 49 Page - Texas Instruments

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