ES4118F datasheet(3/4 Pages) ETC

3 / 4 page

SAM0422-052901

ESS Technology, Inc.

ES4118 PRODUCT BRIEF

ES4118 PIN DESCRIPTION

Table 1 lists the ES4118 pin descriptions.

Table 1

ES4118 Pin Descriptions List

Name

Number

I/O

Definition

VCC

1, 9, 18, 27, 35, 44,

51, 59, 68, 75, 83, 92,

99, 104, 111, 121, 130,

139, 148, 157, 164,

172, 183, 193, 201

3.3V power supply.

LA[21:0]

7:2, 16:10, 23:19,

207:204

Device address output.

VSS

8, 17, 26, 34, 43, 52,

60, 67, 76, 84, 91, 98,

103, 112, 120, 129,

138, 147, 156, 163,

171, 177, 184, 192,

200, 208

Ground.

RESET#

Reset input, active low.

TDMDX

TDM transmit data.

RSEL

ROM Select.

TDMDR

TDM receive data.

TDMCLK

TDM clock input.

TDMFS

TDM frame sync.

TDMTSC#

TDM output enable.

TWS

Audio transmit frame sync.

TSD

Audio transmit serial data port.

SEL_PLL0

Select PLL0:

SEL_PLL2

Select PLL2. (Refer to the definitions table in pin number 33.)

37, 38, 41, 42,

142:146, 149:155,

158, 202, 203

No connect.

MCLK

I/O

Audio master clock for audio DAC.

TBCK

I/O

Audio transmit bit clock.

RSD

Audio receive serial data.

RWS

Audio receive frame sync.

RBCK

Audio receive bit clock.

APLLCAP

Analog PLL capacitor.

XIN

Crystal input.

XOUT

Crystal output.

DMA[11:0]

53:58, 61:66

DRAM address bus.

DCAS#

DRAM column address strobe.

DOE#

DRAM output enable.

DSCK_EN

DRAM clock enable

DWE#

DRAM write enable.

DRAS[2:0]#

74:72

DRAM row address strobe.

DB[15:0]

77:82, 85:90, 93:96

I/O

DRAM data bus.

DCS[1:0]#

97, 100

SDRAM chip select [1:0], active low.

DQM

101

Data input/output mask.

DSCK

102

Clock to SDRAM.

RSEL

Selection

016-bit ROM

8-bit ROM.

SEL_PLL2

SEL_PLL1 SEL_PLL0 Notes

2.5 x DCLK

3 x DCLK

3.5 x DCLK

4 x DCLK.

ES4118F Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers

ES4118F Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4

Datasheet Download

Link URL