ES4118F datasheet(4/4 Pages) ETC

4 / 4 page

SAM0422-052901

ES4118 PRODUCT BRIEF

No part of this publication may be reproduced, stored in a

retrieval system, transmitted, or translated in any form or

by any means, electronic, mechanical, manual, optical, or

otherwise, without the prior written permission of ESS

Technology, Inc.

ESS Technology, Inc. makes no representations or

warranties regarding the content of this document.

All specifications are subject to change without prior

notice.

ESS Technology, Inc. assumes no responsibility for any

errors contained herein.

(P) U.S. Patent 4,214,125 and others, other patents

pending.

VideoDrive

® is a registered trademark of ESS Technology,

Inc.

All other trademarks are owned by their respective

holders and are used for identification purposes only.

ORDERING INFORMATION

DCLK

105

Clock input (bypass/test mode).

YUV[7:0]

106:110, 113:115

8-bit YUV output.

PCLK2XSCN

116

I/O

27 MHz doubled pixel clock.

PCLKQSCN

117

I/O

13.5 MHz pixel clock.

VSYNC#

118

I/O

Vertical sync.

HSYNC#

119

I/O

Horizontal sync.

HD[15:0]

122:128, 131:137,

140:141

I/O

Host data bus.

VPP

159

5V power supply.

AUX[7:0]

160:162, 165:169

I/O

Auxiliary ports.

LOE#

170

Device output enable.

LCS[3:0]#

173:176

Chip select [3:0].

LD[15:0]

178:182, 185:191,

194:197

I/O

Device data bus.

LWRLL#

198

Device write enable.

LWRHL#

199

Device write enable.

Table 1

ES4118 Pin Descriptions List (Continued)

Name

Number

I/O

Definition

Part Number

Description

Package

ES4118F

Super VCD Processor

208-pin PQFP

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