CR16MCS5 datasheet(21/156 Pages) NSC

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8.3.5

Access Timing Summary Table

Table8 is a summary showing the number of access cycles

used for various address ranges.

8.3.6

Recommended Register Settings

Table9 shows the recommended register settings for various

clock rates. Different clock rates require different register set-

tings because the flash EEPROM program memories have

specific setup and hold requirements that can be met only by

using enough wait cycles and hold cycles.

Between clock rates of 10 MHz and 20MHz, the number of

wait states required for memory access (either none or one)

depends on the desired power mode of the program memory.

Table 8

Access Timing Table

Address

Range (hex)

Memory or

I/O Type

Access Cycles

read

write

0000-BFFF

Flash EEPROM Program

Memory

SZCFG0.FRE=1:

1 cycle

SZCFG0.FRE=1:

1 cycle

+ BCFG.EWR

(+ programming time)

SZCFG0.FRE=0:

2 cycles

+ SZCFG0.WAIT

+ SZCFG0.HOLD

SZCFG0.FRE=0:

2 cycles

+ BCFG.EWR

+ SZCFG0.WAIT

+ SZCFG0.HOLD

(+ programming time)

C000-CBFF

Static RAM Memory

1 cycle

F000-F27F

EEPROM Data Memory

MCFG.ZEROWS=1:

1 cycle

MCFG.ZEROWS=1:

1 cycle

(+ programming time)

MCFG.ZEROWS=0:

2 cycles

MCFG.ZEROWS=0:

2 cycles

(+ programming time)

F900-FFFF

F800-F9FF

FC00-FFFF

On-Chip Peripherals

2 cycles

FB00-FBFF

Ports B and C

3 cycle

+ IOCFG.WAIT

+ IOCFG.HOLD

3 cycle

+ BCFG.EW

+ IOCFG.WAIT

+ IOCFG.HOLD

Table 9

Recommended Register Settings

Clock Rate

SZCFG0

SZCFG1

IOCFG

< 10 MHz,

0 wait state

0880 hex

0080 hex

10 to 20MHz,

0 wait state

0880 hex

0080 hex

10 to 20MHz,

1 wait state

0080 hex

> 20 MHz,

1 wait state

0080 hex

CR16MCS5 Datasheet(PDF) 21 Page - National Semiconductor (TI)

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