CR16MCS5 datasheet(39/156 Pages) NSC

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12.0 Dual Clock and Reset

The Dual Clock and Reset module (CLK2RES) generates a

high-speed main system clock from an external crystal net-

work and a slow clock (32.768 kHz or other rate) for operat-

ing the device in Power Save mode. It also provides the main

system reset signal, a power-on reset function, a main clock

prescaler to generate two additional low speed clocks, and

an 32kHz oscillator start-up delay.

Figure7 is block diagram of the Dual Clock and Reset mod-

ule.

12.1

EXTERNAL CRYSTAL NETWORK

An external crystal network is required at pins X1CKI and

X1CKO for the main clock. A similar external crystal network

may be used at pins X2CKI and X2CKO for the slow clock in

packages that have these pins. If an external crystal network

is not used for the slow clock, the clock is generated by divid-

ing the fast main clock.

The crystal oscillator you choose may require external com-

ponents different from the ones specified above. In that case,

consult with National’s engineer for the component specifica-

tions

The crystals and other oscillator components should be

placed close to the X1CKI/X1CLO and X2CKI/X2CLO device

input pins to keep the printed trace lengths to an absolute

minimum.

Figure8 shows the required crystal network at X1CKI/

X1CKO and optional crystal network at X2CKI/X2CKO.

Table13 shows the component specifications for the main

crystal network and Table14 shows the component specifi-

cations for the 32.768 kHz crystal network.

Figure 7.

Dual Clock and Reset Module Block Diagram

8-Bit

14-Bit Timer

6-Bit Timer

Start-Up-Delay

Preset

Power-On-Reset

System

Reset

Stop

Main Osc In

Reset

X1CKI

X1CKO

X2CKI

X2CKO

Main Osc.

32kHz Osc.

Stop Main Osc.

Stop 32kHz Osc.

Main Clk

Good Main

Clk

Low Speed

Clk

Good Low

Speed Clk

Stop Low

Speed Clk

Time-out

Prescaler

Div.

by-2

4-Bit

Prescaler

2 Low

Speed Clk

4-Bit

Prescaler

Outputs

CR16MCS5 Datasheet(PDF) 39 Page - National Semiconductor (TI)

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