LMD18400 datasheet(8/18 Pages) NSC

8 / 18 page

Applications Information (Continued)

PROTECTION CIRCUITRY

The LMD18400 has extensive protection circuitry built in

With any power device protection against excessive volt-

age current and temperature conditions is essential To

achieve a ‘‘fail-safe’’ system implementation the loads are

deactivated automatically by the LMD18400 in the event of

any detected overvoltage or over-temperature fault condi-

tions

Voltage Protection

The VCC supply can range from b05V to a60 VDC without

any damage to the LMD18400 The CMOS logic circuitry is

biased from an internal 51V regulator which protects these

lower voltage transistors from the higher VCC potentials In

order to protect the loads connected to the switch outputs

however an overvoltage shutdown circuit is employed

Should the VCC potential exceed 35V all of the switches are

turned OFF thereby disconnecting the loads This 35V

threshold has 750 mV of hysteresis to prevent potential os-

cillations

Additionally there is an undervoltage lockout feature built

in With VCC less than 5V it becomes uncertain whether the

logic circuitry can hold the switches in their commanded

state To avoid this uncertainty all of the switches are

turned OFF when VCC drops below approximately 5V

Figure 3 illustrates the shutoff of an output during a 0V to

80V VCC supply transient

OverUnder

Voltage Shutdown

TLH11026 – 12

FIGURE 3 OvervoltageUndervoltage Shutdown

The LMD18400 has been designed to drive all types of

loads When driving a ground referenced inductive load

such as a relay or solenoid the voltage across the load will

reverse in polarity as the field in the inductor collapses when

the power switch is turned OFF This will pull the output pin

of the LMD18400 below ground This negative transient

voltage is clamped at approximately b5V to protect the IC

This clamping action is not done with diodes but rather the

power DMOS switch turning back on momentarily to con-

duct the inductor current as it de-energizes as shown in

Figure 4

TLH11026 – 13

FIGURE 4 Turn-OFF Conditions with an Inductive Load

When the output inductance produces a negative voltage

the gate of the DMOS transistor is clamped at 0V At

35V the source of the power device is less than the gate

by enough to cause the switch to turn ON again During this

negative transient condition the power limiting circuitry to

protect the switch is disabled due to the gate being held at

0V The maximum current during this clamping interval

which is equal to the steady state ON current through the

inductor should be kept less than 1A Another concern dur-

ing this interval has to do with the size of an inductive load

and the amount of time required to de-energize it With larg-

er inductors it may be possible for the additional power dis-

sipation to cause the die temperaure to exceed the thermal

shutdown limit If this occurs all of the other switches will

turn OFF momentarily (see section on Thermal Manage-

ment)

Power Limiting

The LMD18400 utilizes a true instantaneous power limit cir-

cuit rather than simple current limiting to protect each

switch This provides a higher transient current capability

while still maintaining a safe power dissipation level The

power dissipation in each switch (the product of the Drain-to

Source voltage and the output current Vds c IOUT) is con-

http

www nationalcom

LMD18400 Datasheet(PDF) 8 Page - National Semiconductor (TI)

LMD18400 Datasheet(HTML) 8 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Datasheet Download

Link URL