CHRONTEL

CH7002D

26

201-0000-029 Rev6.1, 8/2/99

The Connection Detect Register provides a means to sense the connection of a TV to either S-Video or composite

video outputs. The status bits, Y, C, and CVBS, correspond to both the DAC outputs for S-Video (Y and C outputs)

and composite video (CVBS). However, the values contained in these status bits ARE NOT VALID until a sensing

procedure is performed. Using this register requires a sequence of events to enable the sensing of outputs, then

reading out the applicable status bits. The detection sequence works as follows:

1. Set the SENSE bit to a 1. This forces a constant current output onto the Y, C, and CVBS outputs. Note that

during SENSE = 1, these 3 analog outputs are at steady state and no TV synchronization pulses are asserted.

2. Reset the SENSE bit to 0. This triggers a comparison between the voltage sensed on these analog outputs

and the reference value expected (Vthreshold = 1.235V). If the measured voltage is below this threshold

value, it is considered connected. If it is above this voltage, it is considered unconnected. During this step,

each of the three status bits corresponding to individual analog outputs will be set if they are NOT

CONNECTED.

3. Read the status bits. The status bits, Y, C, and CVBS (corresponding to S-Video Y and C outputs and

composite video) now contain valid information which can be read to determine which outputs are

connected to a TV. Again, a “0” indicates a valid connection, a “1” indicates an unconnected output.

Test Register

Symbol: TR

Address: 0AH

Bits: 8

The Test Register contains 8 bits which are reserved for implementing patterns and measurements for tests. Writing

a logical one into each bit, in this register, places the chip in a specific test mode. These test modes are not

documented for use herein, since they are used only for manufacturing test.

Address Register

Symbol: AR

Address: 0BH

Bits: 4

The Address Register points to the register currently being accessed.

Since the most significant four bits of all

addresses are zero, this register contains only the four least significant bits, AR[3:0].

Bit:

7

6

5

4

3

2

1

0

Symbol:

T7

T6

T5

T4

T3

T2

T1

T0

Type:

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Default:

0

0

0

0

0

0

0

0

Bit:

7

6

5

4

3

2

1

0

Symbol:

AR3

AR2

AR1

AR0

Type:

R/W

R/W

R/W

R/W

Default:

0

0

0

0

X

X

X

X