AD7779ACPZ datasheet(4/101 Pages) AD

4 / 101 page

Data Sheet

AD7779

Rev. A | Page 3 of 100

Channel 1 Offset Upper Byte Register .....................................78

Channel 1 Offset Middle Byte Register....................................78

Channel 1 Offset Lower Byte Register .....................................78

Channel 1 Gain Upper Byte Register........................................78

Channel 1 Gain Middle Byte Register......................................79

Channel 1 Gain Lower Byte Register........................................79

Channel 2 Offset Upper Byte Register .....................................79

Channel 2 Offset Middle Byte Register....................................79

Channel 2 Offset Lower Byte Register .....................................80

Channel 2 Gain Upper Byte Register........................................80

Channel 2 Gain Middle Byte Register......................................80

Channel 2 Gain Lower Byte Register........................................80

Channel 3 Offset Upper Byte Register .....................................81

Channel 3 Offset Middle Byte Register....................................81

Channel 3 Offset Lower Byte Register .....................................81

Channel 3 Gain Upper Byte Register........................................81

Channel 3 Gain Middle Byte Register......................................82

Channel 3 Gain Lower Byte Register........................................82

Channel 4 Offset Upper Byte Register .....................................82

Channel 4 Offset Middle Byte Register....................................82

Channel 4 Offset Lower Byte Register .....................................83

Channel 4 Gain Upper Byte Register........................................83

Channel 4 Gain Middle Byte Register......................................83

Channel 4 Gain Lower Byte Register........................................83

Channel 5 Offset Upper Byte Register .....................................84

Channel 5 Offset Middle Byte Register....................................84

Channel 5 Offset Lower Byte Register .....................................84

Channel 5 Gain Upper Byte Register........................................84

Channel 5 Gain Middle Byte Register......................................85

Channel 5 Gain Lower Byte Register........................................85

Channel 6 Offset Upper Byte Register .....................................85

Channel 6 Offset Middle Byte Register....................................85

Channel 6 Offset Lower Byte Register .....................................86

Channel 6 Gain Upper Byte Register........................................86

Channel 6 Gain Middle Byte Register......................................86

Channel 6 Gain Lower Byte Register .......................................86

Channel 7 Offset Upper Byte Register .....................................87

Channel 7 Offset Middle Byte Register....................................87

Channel 7 Offset Lower Byte Register .....................................87

Channel 7 Gain Upper Byte Register .......................................87

Channel 7 Gain Middle Byte Register......................................88

Channel 7 Gain Lower Byte Register .......................................88

Channel 0 Status Register ..........................................................88

Channel 1 Status Register ..........................................................89

Channel 2 Status Register ..........................................................89

Channel 3 Status Register ..........................................................90

Channel 4 Status Register ..........................................................90

Channel 5 Status Register ..........................................................91

Channel 6 Status Register ..........................................................91

Channel 7 Status Register ..........................................................92

Channel 0/Channel 1 DSP Errors Register..............................92

Channel 2/Channel 3 DSP Errors Register..............................93

Channel 4/Channel 5 DSP Errors Register..............................93

Channel 6/Channel 7 DSP Errors Register..............................94

Channel 0 to Channel 7 Error Register Enable Register .......94

General Errors Register 1...........................................................95

General Errors Register 1 Enable..............................................95

General Errors Register 2...........................................................96

General Errors Register 2 Enable..............................................96

Error Status Register 1................................................................97

Error Status Register 2................................................................97

Error Status Register 3................................................................98

Decimation Rate (N) MSB Register .........................................98

Decimation Rate (N) LSB Register...........................................98

Decimation Rate (IF) MSB Register.........................................99

Decimation Rate (IF) LSB Register ..........................................99

SRC Load Source and Load Update Register..........................99

Outline Dimensions......................................................................100

Ordering Guide .........................................................................100

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