MT8880CSSLASHCS-1 datasheet(8/18 Pages) MITEL

8 / 18 page

MT8880C/MT8880C-1 ISO2-CMOS

4-40

Equation 1. THD (%) For a Single Tone

Equation 2. THD (%) For a Dual Tone

Table 1. Actual Frequencies Versus Standard

Requirements

using Equation 2. VL and VH correspond to the low

group

amplitude

and

high

group

amplitude,

respectively, and V2IMD is the sum of all the

intermodulation components. The internal switched-

capacitor filter following the D/A converter keeps

distortion products down to a very low level as

shown in Figure 10.

DTMF Clock Circuit

The internal clock circuit is completed with the

addition of a standard television colour burst crystal.

The crystal specification is as follows:

Frequency:

3.579545 MHz

Frequency Tolerance:

0.1%

Resonance Mode:

Parallel

Load Capacitance:

18pF

ACTIVE

INPUT

OUTPUT FREQUENCY

(Hz)

%ERROR

SPECIFIED

ACTUAL

697

699.1

+0.30

770

766.2

-0.49

852

847.4

-0.54

941

948.0

+0.74

1209

1215.9

+0.57

1336

1331.7

-0.32

1477

1471.9

-0.35

1633

1645.0

+0.73

THD(%) =

100

Vfundamental

V22f + V

3f + V

4f + .... V

V2L + V

V22L + V

3L + .... V

nL + V

2H +

3H + .. V

nH + V

IMD

THD (%) = 100

Maximum Series Resistance:150 ohms

Maximum Drive Level:

2mW

e.g.

CTS Knights MP036S

Toyocom TQC-203-A-9S

number

MT8880C/C-1

devices

can

connected as shown in Figure 12 such that only one

crystal is required. Alternatively, the OSC1 inputs on

all devices can be driven from a TTL buffer with the

OSC2 outputs left unconnected.

Figure 12 - Common Crystal Connection

Microprocessor Interface

The

MT8880C/C-1

employs

microprocessor

interface which allows precise control of transmitter

and receiver functions. There are five internal

registers

associated

with

the

microprocessor

interface

which

can

subdivided

into

three

categories, i.e., data transfer, transceiver control and

transceiver

status.

There

are

two

registers

associated with data transfer operations.

The Receive Data Register contains the output code

of the last valid DTMF tone pair to be decoded and is

a read only register. The data entered in the Transmit

Data Register will determine which tone pair is to be

generated (see Figure 7 for coding details). Data can

only be written to the transmit register. Transceiver

control is accomplished with two Control Registers

(CRA and CRB) which occupy the same address

space. A write operation to CRB can be executed by

setting the appropriate bit in CRA. The following

write operation to the same address will then be

directed to CRB and subsequent write cycles will

then be directed back to CRA. A software reset must

be included at the beginning of all programs to

initialize the control and status registers after power

up or power reset (see Figure 16). Refer to Tables 3,

4, 5 and 6 for details concerning the Control

Registers. The IRQ/CP pin can be programmed such

that it will provide an interrupt request signal upon

validation of DTMF signals or when the transmitter is

ready for more data (Burst mode only). The IRQ/CP

pin is configured as an open drain output device and

as such requires a pull-up resistor (see Figure 13).

MT8880C/C-1

OSC1

OSC2

MT8880C/C-1

OSC1

OSC2

MT8880C/C-1

OSC1

OSC2

3.579545 MHz

MT8880CS/CS-1 Datasheet(PDF) 8 Page - Mitel Networks Corporation

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