PCI7621 datasheet(266/298 Pages) TI

266 / 298 page

12−12

12.18 Power Management Capabilities Register

The power management capabilities register indicates the capabilities of the SD host controller related to PCI power

management. See Table 12−13 for a complete description of the register contents.

Bit

Name

Power management capabilities

Type

Default

Power management capabilities

Offset:

82h

Type:

Read/Update, Read-only

Default:

7E02h

Table 12−13. Power Management Capabilities Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

PME_D3COLD

PME support from D3cold. This bit can be set to 1 or cleared to 0 via bit 4 (D3_COLD) in the general

control register at offset 88h in the PCI configuration space (see Section 12.22). When this bit is set

to 1, it indicates that the SD host controller is capable of generating a PME wake event from D3cold.

This bit state is dependent upon the SD host controller VAUX implementation and may be configured

by using bit 4 (D3_COLD) in the general control register (see Section 12.22).

14−11

PME_SUPPORT

PME support. This 4-bit field indicates the power states from which the SD host controller may assert

PME. This field returns a value of 1111b by default, indicating that PME may be asserted from

the D3hot, D2, D1, and D0 power states.

D2_SUPPORT

D2 support. Bit 10 is hardwired to 1, indicating that the SD host controller supports the D2 power state.

D1_SUPPORT

D1 support. Bit 9 is hardwired to 1, indicating that the SD host controller supports the D1 power state.

8−6

AUX_CURRENT

3.3-VAUX auxiliary current requirements. This requirement is design dependent.

DSI

Device-specific initialization. This bit returns 0 when read, indicating that the SD host controller does

not require special initialization beyond the standard PCI configuration header before a generic class

driver is able to use it.

RSVD

Reserved. Bit 4 returns 0 when read.

PME_CLK

PME clock. This bit returns 0 when read, indicating that the PCI clock is not required for the SD host

controller to generate PME.

2−0

PM_VERSION

Power-management version. This field returns 010b when read, indicating that the SD host controller

is compatible with the registers described in the PCI Bus Power Management Interface Specification

(Revision 1.1).

PCI7621 Datasheet(PDF) 266 Page - Texas Instruments

PCI7621 Datasheet(HTML) 266 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL