LMX2355TM datasheet(11/23 Pages) NSC

11 / 23 page

Functional Description (Continued)

LMX2354 RF N Counter Register in Fractional Mode with P = 8/9/12/13

C Word

B Word

A Word

Fractional Word

987

5432

1–23

Divide ratios less than 24 are impossible since it is required that C

≥3

These bits are used for

the fractional word when

the part is operated in

fractional mode

24–39

Some of these values are legal divide ratios, some are not

40*

000000

0100

000000

0100

...

272

000001

1000

...

......

....

16,383

111111

1101

*Minimum continuous divide ratio is P

•[MAX{A,B}+2]

1.3.1 Prescaler

The RF and IF inputs to the prescaler consist of fin and /fin;

which are complimentary inputs to differential pair amplifiers.

The complimentary inputs are internally coupled to ground

with a 10 pF capacitor. These inputs are typically AC coupled

to ground through external capacitors as well. The input

buffer drives the A counter’s ECL D-type flip flops in a dual

modulus configuration. An 8/9/12/13 or 16/17/20/21 prescale

ratio can be selected for the LMX2354. The IF circuitry for

both the LMX2354 contains an 8/9 prescaler. The prescaler

clocks the subsequent CMOS flip-flop chain comprising the

fully programmable A and B counters.

1.3.2 Fractional Compensation

The fractional compensation circuitry of the LMX2354 RF

dividers allows the user to adjust the VCO’s tuning resolution

in 1/16 or 1/15 increments of the phase detector comparison

frequency. A 4-bit register is programmed with the fractions

desired numerator, while another bit selects between frac-

tional 15 and 16 modulo base denominator (see program-

ming description 5.2.3). An integer average is accomplished

by using a 4-bit accumulator. A variable phase delay stage

compensates for the accumulated integer phase error, mini-

mizing the charge pump duty cycle, and reducing spurious

levels. This technique eliminates the need for compensation

current injection in to the loop filter. Overflow signals gener-

ated by the accumulator are equivalent to 1 full VCO cycle,

and result in a pulse swallow.

1.4 PHASE/FREQUENCY DETECTOR

The RF and IF phase/frequency detectors are driven from

their respective N and R counter outputs. The phase detec-

tor outputs control the charge pumps. The polarity of the

pump-up or pump-down control is programmed using

RF_PD_POL or IF_PD_POL depending on whether RF/IF

VCO characteristics are positive or negative (see program-

ming descriptions 4.1.4 and 4.2.2). The phase detector also

receives a feedback signal from the charge pump, in order to

eliminate dead zone.

1.5 CHARGE PUMP

The phase detector’s current source outputs pump charge

into an external loop filter, which then converts the charge

into the VCO’s control voltage. The charge pumps steer the

charge pump output, CPo, to Vcc (pump-up) or ground

(pump-down).

When

locked,

CPo

primarily

TRI-STATE® mode with small corrections. The RF charge

pump output current magnitude is programmable from

100 µA to 1.6 mA in 100 µA steps as shown in table in

programming description 4.2.2. The IF charge pump is set to

either 100 µA or 800 µA levels using bit IF_R [19] (see

programming description 4.1.4).

1.6 VOLTAGE DOUBLER

The V

pRF pin is normally driven from an external power

supply over a range of V

CC to 5.5V to provide current for the

RF charge pump circuit. An internal voltage doubler circuit

connected between the V

CC and VpRF supply pins alter-

nately allows V

CC =3V(±10%) users to run the RF charge

pump circuit at close to twice the V

CC power supply voltage.

The voltage doubler mode is enabled by setting the V2_EN

bit (RF_R [22]) to a HIGH level. The voltage doubler’s

charge pump driver originates from the RF oscillator input

(OSC

RF). The average delivery current of the doubler is less

than the instantaneous current demand of the RF charge

pump when active and is thus not capable of sustaining a

continuous out of lock condition. A large external capacitor

connected to V

pRF (≈0.1 µF) is therefore needed to control

power supply droop when changing frequencies.

1.7 MICROWIRE™ SERIAL INTERFACE

The programmable functions are accessed through the MI-

CROWIRE serial interface. The interface is made of 3 func-

tions: clock, data and latch enable (LE). Serial data for the

various counters is clocked in from data on the rising edge of

clock, into the 24-bit shift register. Data is entered MSB first.

The last two bits decode the internal register address. On the

rising edge of LE, data stored in the shift register is loaded

into one of the 4 appropriate latches (selected by address

bits). A complete programming description is included in the

following sections.

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