5.1.2 CMOS (Programmable CMOS outputs)

(IF_N[17]–IF_N[20])

MSB

LSB

FastLock

TEST

OUT_1

OUT_0

Note: Test bit is reserved and should be set to zero for normal usage.

5.1.3 Programmable CMOS Output Truth Table

Bit

Location

Function

0

1

OUT_0

IF_N[17]

OUT0 CMOS Output Pin

Level Set

LOW

HIGH

OUT_1

IF_N[18]

OUT1 CMOS Output Pin

Level Set

LOW

HIGH

Test

IF_N[19]

Fractional Test Bit

Normal Operation

No Fractional

Compensation

Fastlock

IF_N[20]

Fastlock Mode Select

CMOS Output

Fastlock Mode

Test Bit IF_N[19] controls the fractional spur compensation and should be set to 0 for normal operation. If the test bit is set to 1,

then the fractional spurs become much worse, but the phase noise improves about 5 dB.

When the Fastlock bit is set to 1, OUT_0 and OUT_1 are don’t care bits. Fastlock mode utilizes the OUT0 and OUT1 output pins

to synchronously switch between active low and TRI-STATE. The OUT0 = LOW state occurs whenever the RF loop’s CP_8X is

selected HIGH while the Fastlock bit is set HIGH (see programming description 4.2.2). The OUT0 pin reverts to TRI-STATE when

the CP_8X bit is LOW. Similarly for the IF loop, the synchronous activation of OUT1 = LOW or TRI-STATE, is dependent on

whether the CP_GAIN_8 is high or low respectively (see programming description 4.1.4).

5.1.4 3-BIT IF SWALLOW COUNTER DIVIDE RATIO (IF A COUNTER)

(IF_N[2]−IF_N[4])

Swallow Count

IF_NA_CNTR

(A)

2

1

0

00

00

10

01

••

••

71

11

Note: Swallow Counter Value: 0 to 7

IF_NB_CNTR

≥ IF_NA_CNTR

Minimum continuous count = 56 ( A=0, B=7)

5.1.5 12-BIT IF PROGRAMMABLE COUNTER DIVIDE RATIO (IF B COUNTER)

(IF_N[5]–IF_N[16])

IF_NB_CNTR

Divide

Ratio

11

10

987654321

0

3

00000000001

1

4

00000000010

0

•

•••••••••••

•

4095

11111111111

1

Note: Divide ratio: 3 to 4095 (Divide ratios less than 3 are prohibited)

IF_NB_CNTR

≥ IF_NA_CNTR

N divider continuous integer divide ratio 56 to 32,767.

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