4.2.1 (RF_R[22]–RF_R[23])

DLL_MODE

V2_EN

BIT

LOCATION

FUNCTION

0

1

DLL_MODE

RF_R [23]

Delay Line Loop

Calibration Mode

Slow

Fast

V2_EN

RF_R [22]

RF_Voltage Doubler

Enable

Disabled

Enabled

Note 1. V2_EN bit when set high enables the voltage doubler for the RF Charge Pump supply.

Note 2. DLL_MODE bit should be set to one for normal usage.

4.2.2 RF_CP_WORD

(RF_R[17]–RF_R[21])

CP_8X

CP_4X

CP_2X

CP_1X

RF_PD_POL

RF_PD_POL ( RF_R[17] ) should be set to one when RF VCO characteristics are positive. When RF VCO frequency decreases

with increasing control voltage RF_PD_POL should be set to zero.

CP_1X, CP_2X, CP_4X, and CP_8X are used to step the RF Charge Pump output current magnitude from 100 µA to 1.6 mA in

100 µA steps as shown in the table below.

RF Charge Pump Output Truth Table

ICPo µA (typ)

CP8X

RF_R[21]

CP4X

RF_R[20]

CP2X

RF_R[19]

CP1X

RF_R[18]

100

0

0

0

0

200

0

0

0

1

300

0

0

1

0

400

0

0

1

1

•

•••

•

900

1

0

0

0

•

•••

•

1600

1

1

1

1

5.0 Programmable Dividers (N Counters)

5.1 IF_N REGISTER

If the Control Bits (CTL [1:0]) are 0 1, data is transferred from the 24-bit shift register into the IF_N register latch which sets the

PLL’s 15-bit programmable N counter value and various control functions. The IF_N counter consists of the 3-bit swallow counter

(A counter), and the 12-bit programmable counter (B counter). Serial data format is shown below in tables 5.1.3 and 5.1.4. The

divide ratio (IF_NB_CNTR) must be

≥ 3. The divide ratio is programmed using the bits IF_N_CNTR as shown in tables 5.1.2 and

5.1.3. The minimum continuous divide ratio is 56. The CMOS [3:0] bits program the 2 CMOS outputs detailed in section 5.1.2, and

also contain the fractional test bit.

MSB

LSB

IF_CTL_WORD [2:0]

CMOS [3:0]

IF_NB_CNTR [11:0]

IF_NA_CNTR [2:0]

0

1

23

21 20

17 16

5 4

2 1

0

5.1.1 IF_CTL_WORD

(IF_N[21]–IF_N[23])

MSB

LSB

IF_CNT_RST

PWDN_IF

PWDN_MODE

Note: See section 5.2.1.2 for IF control word truth table.

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