LMX2372TM datasheet(5/16 Pages) NSC

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Electrical Characteristics (V

CC = Vp = Vµc = 3.0V; −40˚C < TA < 85˚C except as specified). (Continued)

CHARGE PUMP

Value

Unit

Symbol

Parameter

Conditions

Min

Typ

Max

ICP

o-source

Main and Auxiliary Charge

Pump Output Current (Note 4)

VCP

o = Vp/2, ICPo_4X = 0

1.0

ICP

o-sink

VCP

o = Vp/2, ICPo_4X = 0

−1.0

ICP

o-source

VCP

o = Vp/2, ICPo_4X = 1

4.0

ICP

o-sink

VCP

o = Vp/2, ICPo_4X = 1

−4.0

ICP

o-TRI

Charge Pump TRI-STATE®

Current

0.5

≤ VCP

o ≤ Vp − 0.5,

−40˚C < T

A < 85˚C

−2.5

0.1

2.5

ICP

o-sink vs

ICP

o-source

CP Sink vs Source Mismatch

VCP

o = Vp/2, TA = 25˚C

310

ICP

o vs

VCP

CP Current vs Voltage

0.5

≤ VCP

o ≤ Vp − 0.5, TA = 25˚C

815

ICP

o vs TA

CP Current vs Temperature

VCP

o = Vp/2, −40˚C < TA < 85˚C

DIGITAL INTERFACE (DATA, CLOCK, LE)

Value

Unit

Symbol

Parameter

Conditions

Min

Typ

Max

High-Level Input Voltage

Vµc = 1.72V to 5.5V

0.8 Vµc

Low-Level Input Voltage

Vµc = 1.72V to 5.5V

0.2 Vµc

High-Level Input Current

IH = Vµc = 5.5V

−1.0

1.0

µA

Low-Level Input Current

IL = 0, Vµc = 5.5V

−1.0

1.0

µA

Low-Level Output Current

OL = 1.0 mA, VEXT = 1.8V (Note

0.1

0.4

MICROWIRE TIMING

Value

Unit

Symbol

Parameter

Conditions

Min

Typ

Max

Data to Clock Setup Time

See Data Input Timing

Data to Clock Hold Time

See Data Input Timing

CWH

Clock Pulse Width High

See Data Input Timing

CWL

Clock Pulse Width Low

See Data Input Timing

Clock to Load Enable Setup

Time

See Data Input Timing

Load Enable Pulse Width

See Data Input Timing

Note 4: Main and Auxiliary Charge Pump magnitude are controlled by Main_ICPo_4X and Aux_ICPo_4X bits respectively.

Note 5: Lock Detect open drain output only pulled up to VEXT. Typically VEXT = VCC.

1.0 Functional Description

The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a frequency synthesizer

such as the National Semiconductor LMX2370/2371/2372, a voltage controlled oscillator (VCO), and a passive loop filter. The fre-

quency synthesizer includes a phase detector, a current mode charge pump, as well as programmable reference [R] and feed-

back [N] frequency dividers. The VCO frequency is established by dividing the crystal reference signal down via the R-counter to

obtain a comparison reference frequency. This reference signal (

R) is then presented to the input of a phase/frequency detector

and compared with the feedback signal (

N), which is obtained by dividing the VCO frequency down by way of the N-counter. The

phase/frequency detector’s current source output pumps charge into the loop filter, which then integrates into the VCO’s control

voltage. The function of the phase/frequency comparator is to adjust the control voltage presented to the VCO until the feedback

signal frequency and phase match that of the reference signal. When this “Phase-Locked” condition exists, the VCO frequency

will be N times that of the comparison frequency, where N is the integer divide ratio.

1.1 REFERENCE OSCILLATOR INPUT

The reference oscillator frequency for the Main and Auxiliary PLLs is provided from the external reference through the OSC

in pin.

OSC

in can operate up to 50 MHz with input sensitivity of 0.5 VPP. The OSCin pin drives both the Main R-counter and the Auxiliary

R-counter. The input has a V

CC/2 input threshold that can be driven from an external CMOS or TTL logic gate. Typically, the OSCin

is connected to the output of a crystal oscillator.

1.2 REFERENCE DIVIDERS (R-COUNTERS)

The Main and Auxiliary R-counters are both clocked through the oscillator block in common. The maximum frequency is 50 MHz.

Both R-counters are CMOS design and 15-bit in length with programmable divider ratio from 2 to 32,767.

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