Most Significant Bit

SHIFT REGISTER BIT LOCATION

Least Significant Bit

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

65432

1

0

Data Field

Address Field

Aux_N

Aux_B_CNTR[12:0]

Aux_A_CNTR[4:0]

01

2.3.2 Main_N Register

If the ADDRESS[1:0] field is set to 1 1, data is transferred from the 22-bit shift register into the Main_N register which sets the

Main PLL’s 18-bit N-counter, prescaler value and power-down bit. The 18-bit N-counter consists of a 5-bit swallow counter,

Main_A_CNTR[4:0], and a 13-bit programmable counter, Main_B_CNTR[12:0]. Serial data format is shown below.

Most Significant Bit

SHIFT REGISTER BIT LOCATION

Least Significant Bit

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

65432

1

0

Data Field

Address Field

Main_N

Main_B_CNTR[12:0]

Main_A_CNTR[4:0]

11

2.3.3 Feedback Divide Ratio (Main B Counter, Auxiliary B Counter)

Main_B_CNTR[12:0] or Aux_B_CNTR[12:0]

Divide Ratio

N17

N16

N15

N14

N13

N12

N11

N10

N9

N8

N7

N6

N5

3

00000000

00011

4

00000000

00101

•

••••••••

•••••

8,191

11111111

11111

Note: B-counter divide ratio must be

≥ 3.

2.3.4 Swallow Counter Divide Ratio (Main A Counter, Auxiliary A Counter)

Main_A_CNTR[4:0] or Aux_A_CNTR[4:0]

Divide Ratio

Main_N4

Main_N3

Main_N2

Main_N1

Main_N0

0

00000

1

00001

•

•••••

31

11111

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