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LP3927 Datasheet(PDF) 15 Page - National Semiconductor (TI) |
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LP3927 Datasheet(HTML) 15 Page - National Semiconductor (TI) |
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15 / 16 page ![]() Application Hints (Continued) surement, junction to ambient thermal resistance ( θ JA) can be improved by as much as two times if a LLP is soldered on the board with thermal land and thermal vias than if not. Consider the following equation: Where P is the power dissipated, T J is the maximum junction temperature of the die, T A is the ambient temperature, and θ JA is the thermal resistance of the package. TJ is specified at 150˚C. According to the above equation, in the case where the LP3927 is dissipating 3W of power, T A is limited to 32.6˚C when T J of 125˚C and θ JA of 30.8˚C/W are used in the equation. In order to operate at a higher ambient tempera- ture, power dissipation has to be reduced. A curve of maxi- mum power dissipation vs ambient temperature is provided below. Power Dissipation vs Ambient Temperature ( θ JA=30.8˚C/W) 20037915 Layout Consideration The LP3927 has an exposed die attach pad located at the bottom center of the LLP package. It is imperative to create a thermal land on the PCB board when designing a PCB layout for the LLP package. The thermal land helps to con- duct heat away from the die, and the land should be the same dimension as the exposed pad on the bottom of the LLP (1:1 ratio). The land should be on both the top and the bottom layer of the PCB board. In addition, thermal vias should be added inside the thermal land to conduct more heat away from the surface of the PCB to the ground plane. Typical pitch and outer diameter for these thermal vias are 1.27 mm and 0.33 mm respectively. Typical copper via barrel plating is 1 oz. although thicker copper may be used to improve thermal performance. The LP3927 bottom pad is connected to ground. Therefore, the thermal land and vias on the PCB board need to be connected to ground. For more information on board layout techniques, refer to Application Note 1187 “Leadless Leadframe Package (LLP).” The application note also discusses package han- dling, solder stencil, and assembly process. www.national.com 15 |
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