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ML620Q136B Datasheet(PDF) 12 Page - LAPIS Semiconductor Co., Ltd.

Part # ML620Q136B
Description  16-bit micro controller
PDF  34 Pages
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Manufacturer  LAPIS [LAPIS Semiconductor Co., Ltd.]
Direct Link  http://www.lapis-semi.com/
Logo LAPIS - LAPIS Semiconductor Co., Ltd.

ML620Q136B Datasheet(HTML) 12 Page - LAPIS Semiconductor Co., Ltd.

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FEDL620Q130B-01
ML620Q131B/2B/3B/4B/5B/6B
12/34
PIN DESCRIPTION
Table 2 Pin Description (1/4)
Pin name
I/O
Description
Primary/
Secondary/
Tertiary/
Quartic
Logic
System
RESET_N
I
Reset input pin. When this pin is set to a "L" level, system reset mode is set and
the internal section is initialized. When this pin is set to a "H" level
subsequently, program execution starts.
The RESET_N pin does not have an internal pull-up resistor.
—
Negative
OSC0
I
Crystal connection pin for the high-speed clock.
A crystal oscillator is connected to this pin (4 MHz max.), and capacitors CDH
and CGH (see measurement circuit 1) are connected between this pin and VSS.
This pin is used as the secondary function of the PB2 and PB3 pins.
Secondary
—
OSC1
O
Secondary
—
LSCLK
O
Low-speed clock output. This pin is used as the tertiary function of the PA1 pin
or the secondary function of the PB6 pin.
Secondary/
Tertiary
—
OUTCLK
O
High-speed clock output pin. This pin is used as the tertiary function of the PA0
pin or the secondary function of the PB5 pin.
Tertiary
—
General-purpose input port
PA2
I
General-purpose input port.
—
Positive
General-purpose input/output port
PA0 to PA1
PB0
∼PB7
I/O General-purpose input/output port.
This cannot be used as the general input/output port when used as the
secondary to quartic functions.
—
Positive
PA3 to PA6
I/O General-purpose input/output port.
This cannot be used as the general input/output port when used as the
secondary to quartic functions.
Not available in ML620Q131B/ML620Q132B/ML620Q133B.
—
Positive
Serial (UART)
TXD0
O
UART0 transmit pin. This pin is used as the tertiary function of the PB1 and
PB4 pins.
Tertiary
Positive
TXD1
O
UART1 transmit pin. This pin is used as the secondary function of the PB1,
PB4, and PB7 pins.
Secondary
Positive
RXD0
I
UART0 receive pin. This pin is used as the primary function of the PB0 and
PB5 pins.
Primary
Positive
RXD1
I
UART1 receive pin. This pin is used as the primary function of the PA0 and
PB6 pins.
Primary
Positive
I
2C Bus Interface
SDA
I/O NMOS open drain pin for I
2C data input/output.
This pin is used as the quartic function of the PA0 pin, the tertiary function of
the PA3 pin, or the quartic function of the PB6 pin. A pull-up resistor is
connected externally.
Tertiary/
Quartic
Positive
SCL
I/O NMOS open drain pin for I
2C clock input/output.
This pin is used as the tertiary function of the PA5 pin, the tertiary function of
the PB0 pin, or the tertiary function of the PB7 pin. A pull-up resistor is
connected externally.
Tertiary
Positive



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